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    Method and apparatus for stacking devices in an integrated circuit assembly
    51.
    发明授权
    Method and apparatus for stacking devices in an integrated circuit assembly 有权

    公开(公告)号：US10163675B2

    公开(公告)日：2018-12-25

    申请号：US15629460

    申请日：2017-06-21

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/67 ,  H01L25/065 ,  H01L23/00

    Abstract: Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks.

    Flat Metal Features for Microelectronics Applications
    52.
    发明申请
    Flat Metal Features for Microelectronics Applications 审中-公开

    公开(公告)号：US20180350674A1

    公开(公告)日：2018-12-06

    申请号：US15994435

    申请日：2018-05-31

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L21/768 ,  H01L23/00

    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.

    Ultra High Performance Interposer
    53.
    发明申请
    Ultra High Performance Interposer 审中-公开

    公开(公告)号：US20180331030A1

    公开(公告)日：2018-11-15

    申请号：US16041013

    申请日：2018-07-20

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

    IPC: H01L23/522 ,  H01L23/498 ,  H01L23/48 ,  H01L21/768 ,  H01L21/48 ,  H01L23/14

    CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

    Tall and fine pitch interconnects
    54.
    发明授权
    Tall and fine pitch interconnects 有权

    公开(公告)号：US10103121B2

    公开(公告)日：2018-10-16

    申请号：US15831231

    申请日：2017-12-04

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

    IPC: H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H05K3/34

    Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

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