公开(公告)号：US4626958A

公开(公告)日：1986-12-02

申请号：US811673

申请日：1985-12-20

Applicant: Steven C. Lockard ,  Michael S. Hyslop ,  Jorge M. Hernandez

Inventor： Steven C. Lockard ,  Michael S. Hyslop ,  Jorge M. Hernandez

IPC: H01G2/12 ,  H01G4/228 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H01G1/14 ,  H01L23/02

CPC classification number: H01G4/228 ,  H01G2/12 ,  H05K1/0231 ,  H05K1/18 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K3/3447 ,  Y10S257/916

Abstract: High frequency noise is decoupled from power supplied to a Pin Grid Array (PGA) package by insertion of a decoupling capacitor between the PGA package and printed circuit board. The decoupling capacitor comprises a dielectric material sandwiched between a pair of conductors and having a plurality of leads extending from each conductor. In accordance with the present invention, the decoupling capacitor is individually dimensioned and configured to fit under a PGA package and correspond to the power and ground pin configuration of that PGA package.

Abstract translation: 通过在PGA封装和印刷电路板之间插入去耦电容器，高频噪声与提供给引脚栅极阵列（PGA）封装的电源脱耦。 去耦电容器包括夹在一对导体之间并具有从每个导体延伸的多个引线的电介质材料。 根据本发明，去耦电容器被独立地尺寸设计成配置在PGA封装下并对应于该PGA封装的电源和接地引脚配置。

公开(公告)号：US3500538A

公开(公告)日：1970-03-17

申请号：US3500538D

申请日：1966-08-29

Applicant: GEN ELECTRIC

Inventor： RACITI JOSEPH A

IPC: H05K3/30 ,  H05K3/34 ,  H01R9/06

CPC classification number: B21C3/02 ,  H01R12/58 ,  H05K3/308 ,  H05K3/3405 ,  H05K3/3447 ,  H05K3/3468 ,  H05K2201/0373 ,  H05K2201/09181 ,  H05K2201/10287 ,  H05K2201/10446 ,  H05K2201/10568 ,  H05K2201/10651 ,  H05K2201/10696 ,  H05K2201/10704 ,  H05K2201/1081 ,  H05K2201/2036 ,  Y10T29/49117

公开(公告)号：US3300686A

公开(公告)日：1967-01-24

申请号：US29860363

申请日：1963-07-30

Applicant: IBM

Inventor： JOHNSON ALFRED H ,  MCCONNELL WILLIAM R ,  SCHULZ PETER R

IPC: G06F1/18 ,  H05K1/14

CPC classification number: H05K1/14 ,  G06F1/18 ,  H05K2201/044 ,  H05K2201/09609 ,  H05K2201/10325 ,  H05K2201/10704

公开(公告)号：US20230411365A1

公开(公告)日：2023-12-21

申请号：US18462259

申请日：2023-09-06

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L25/16 ,  H01L23/5386 ,  H05K1/181 ,  H01L2225/1094 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H01L2225/107 ,  H05K2201/10015

Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

公开(公告)号：US20230197696A1

公开(公告)日：2023-06-22

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US20170367180A1

公开(公告)日：2017-12-21

申请号：US15184662

申请日：2016-06-16

Applicant: ALCATEL-LUCENT CANADA INC.

Inventor： James M. SCHRIEL ,  Alex L. CHAN ,  Paul J. BROWN

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K1/0296 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/0005 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) for electrically connecting a discrete array component including a pattern formed on the PCB which is a merger of a set of via pads and a discrete array component; wherein the pattern is generated by a pin mapping between the discrete array component and a via grid array on the PCB; and wherein the pattern is formed of a metal etched during a manufacturing process of the PCB.

公开(公告)号：US20160343646A1

公开(公告)日：2016-11-24

申请号：US14836501

申请日：2015-08-26

Applicant: QUALCOMM Incorporated

Inventor： Reynante Tamunan Alvarado ,  Lizabeth Ann Keser ,  Tong Cui

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/056 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13561 ,  H01L2224/13563 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/381 ,  H05K3/3426 ,  H05K2201/10704 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/0231 ,  H01L2924/01029 ,  H01L2924/07025 ,  H01L2924/067

Abstract: A package (e.g., wafer level package) that includes a die, a redistribution portion coupled to the die, a first high aspect ratio (HAR) interconnect coupled to the redistribution portion of the package, where the first high aspect ratio (HAR) interconnect comprises a width to height ratio of about at least 1:2, and a first solder interconnect coupled to the first high aspect ratio (HAR) interconnect and the redistribution portion. In some implementations, the first high aspect ratio (HAR) interconnect is a composite interconnect that includes a first conductive core and a first conductive layer that at least partially encapsulates the first conductive core. In some implementations, the first conductive layer is a diffusion barrier.

Abstract translation: 包括管芯，耦合到管芯的再分配部分的封装（例如，晶片级封装），耦合到封装的再分配部分的第一高纵横比（HAR）互连，其中第一高纵横比（HAR）互连 包括大约至少1:2的宽高比，以及耦合到第一高纵横比（HAR）互连和再分配部分的第一焊料互连。 在一些实现中，第一高宽比（HAR）互连是复合互连，其包括第一导电芯和至少部分地封装第一导电芯的第一导电层。 在一些实施方案中，第一导电层是扩散阻挡层。

公开(公告)号：US20160309592A1

公开(公告)日：2016-10-20

申请号：US15099905

申请日：2016-04-15

Applicant: Rohm Co., Ltd.

Inventor： Masashi Nagasato

IPC: H05K1/18 ,  H05K1/02

CPC classification number: H05K1/0243 ,  H05K1/0242 ,  H05K1/025 ,  H05K3/4685 ,  H05K2201/09154 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10053 ,  H05K2201/1009 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734

Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.

Abstract translation: 提供了用于抑制寄生成分的印刷线路板。 印刷电路板100包括多层基板110和布置在多层基板110上并与半导体装置10的电源端子排T11a-T11d连接的电力线50.电力线50包括第一布线 形成在多层基板110的表面上的图案51，形成在多层基板110内的第二布线图案52，以及导电第一布线图案51和第二布线图案52旁路的层间连接53x和53y 电力端子排T11a-T11d的至少一部分。

公开(公告)号：US20160233189A1

公开(公告)日：2016-08-11

申请号：US15023716

申请日：2013-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshikazu SHIMOTE ,  Shinji BABA ,  Toshihiro IWASAKI ,  Kazuyuki NAKAGAWA

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49805 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/562 ,  H01L23/564 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16055 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1713 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/85 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/2064 ,  H01L2924/351 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/09427 ,  H05K2201/10704 ,  H05K2201/10977 ,  H05K2203/0465 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/45099 ,  H01L2924/207

Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

Abstract translation: 在根据实施例的半导体器件（SP1）中，与基材层接触的阻焊膜（第一绝缘层SR1）和与该基材层接触的树脂体（第二绝缘层4） 阻焊膜和半导体芯片层叠在布线基板2的基材层（2CR）和半导体芯片（3）之间。 此外，阻焊膜的线膨胀系数等于或大于基材层的线膨胀系数，阻焊膜的线膨胀系数等于或小于 树脂体。 此外，基材层的线膨胀系数小于树脂体的线膨胀系数。 根据上述结构，可以抑制由温度循环负载引起的半导体器件的损坏，从而可以提高可靠性。

公开(公告)号：US08450201B2

公开(公告)日：2013-05-28

申请号：US13167902

申请日：2011-06-24

Applicant: Henning Braunisch ,  Kemal Aygun

Inventor： Henning Braunisch ,  Kemal Aygun

IPC: H01L21/44 ,  H01L23/498 ,  H01R13/62

CPC classification number: H05K1/0243 ,  H01L23/367 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H05K1/182 ,  H05K3/222 ,  H05K2201/10356 ,  H05K2201/10492 ,  H05K2201/10704 ,  Y10T29/49002 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A multimode system with at least two end points may include a multimode signaling path that, in some embodiments, is a multimode cable or a multimode board and is pluggably connectable to packages at each end point. Each end point may include a processor die package coupled to a socket. The socket may also receive a connector that couples the cable to the package. Power supply signals and input/output signals may be decoupled at each end point.

Abstract translation: 具有至少两个端点的多模系统可以包括在一些实施例中是多模电缆或多模板并且可插​​拔地连接到每个端点处的封装的多模信令路径。 每个端点可以包括耦合到插座的处理器管芯封装。 插座还可以接收将电缆耦合到封装的连接器。 电源信号和输入/输出信号可以在每个端点解耦。