公开(公告)号：US20120125670A1

公开(公告)日：2012-05-24

申请号：US13388316

申请日：2010-08-02

申请人： Takahiko Kato ,  Takashi Naito ,  Takuya Aoyagi ,  Hiroki Yamamoto ,  Masato Yoshida ,  Mitsuo Katayose ,  Shinji Takeda ,  Naotaka Tanaka ,  Shuichiro Adachi

发明人： Takahiko Kato ,  Takashi Naito ,  Takuya Aoyagi ,  Hiroki Yamamoto ,  Masato Yoshida ,  Mitsuo Katayose ,  Shinji Takeda ,  Naotaka Tanaka ,  Shuichiro Adachi

IPC分类号： H01B1/02 ,  B22F9/06 ,  H05K1/09

CPC分类号： H01L23/49883 ,  B22F1/0055 ,  B22F1/0074 ,  B22F1/02 ,  C22C1/0425 ,  C22C1/05 ,  H01B1/026 ,  H01J11/12 ,  H01J11/22 ,  H01J2211/225 ,  H01L21/4867 ,  H01L31/022425 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4629 ,  H05K2201/0224 ,  H05K2203/0315 ,  Y02E10/50 ,  H01L2924/00

摘要： In an electronic component having a wiring and/or an electrode prepared through firing of a paste or in an electronic component having a wiring in contact with a glass or glass ceramic member, provided is an electronic component using a Cu-based wiring material which less suffers from increase in electric resistance due to oxidation, which less causes bubbles in the glass or glass ceramic, and has satisfactory migration resistance. The Cu—Al alloy powder includes a Cu—Al alloy powder including Cu and, preferably, 50 percent by weight or less of Al; and an aluminum oxide film having a thickness of 80 nm or less and being present on the surface of the Cu—Al alloy powder. The powder, when compounded with a glass or glass ceramic material to give a paste, can be used to form wiring (interconnections), electrodes, and/or contact members.

摘要翻译： 在具有布线和/或通过烧制制成的电极的电子部件或具有与玻璃或玻璃陶瓷部件接触的布线的电子部件中的电子部件中，提供了使用Cu基布线材料的电子部件 由于氧化而导致的电阻增加，玻璃或玻璃陶瓷中的气泡较少，具有良好的耐迁移性。 Cu-Al合金粉末包括Cu-Cu合金粉末，优选为50重量％以下的Al; 以及Cu-Al合金粉末的表面上存在厚度为80nm以下的氧化铝膜。 当与玻璃或玻璃陶瓷材料混合以得到糊剂时，该粉末可用于形成布线（互连），电极和/或接触构件。

公开(公告)号：US08378459B2

公开(公告)日：2013-02-19

申请号：US12795950

申请日：2010-06-08

申请人： Yasuhiro Naka ,  Naotaka Tanaka ,  Toshihide Uematsu ,  Chuichi Miyazaki ,  Kazunari Suzuki ,  Yasuyuki Nakajima ,  Yoshiyuki Abe ,  Kenji Kohzu ,  Kosuke Kitaichi ,  Shinya Ogane

发明人： Yasuhiro Naka ,  Naotaka Tanaka ,  Toshihide Uematsu ,  Chuichi Miyazaki ,  Kazunari Suzuki ,  Yasuyuki Nakajima ,  Yoshiyuki Abe ,  Kenji Kohzu ,  Kosuke Kitaichi ,  Shinya Ogane

IPC分类号： H01L23/544

CPC分类号： H01L24/11 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05571 ,  H01L2224/05644 ,  H01L2224/06102 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01052 ,  H01L2924/01055 ,  H01L2924/01056 ,  H01L2924/01064 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10158 ,  H01L2924/1306 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014

摘要： In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.

摘要翻译： 在粘合带附着到半导体晶片的主表面上的状态下，在半导体晶片的后表面上形成沟槽。 为了在半导体晶片的后表面中形成沟槽，在半导体晶片的后表面上涂覆抗蚀剂膜之后，通过使用光刻技术对抗蚀剂膜进行构图。 进行抗蚀剂膜的图案化，以便不在要形成沟槽的区域中留下抗蚀剂膜。 然后，通过使用图案化的抗蚀剂膜作为掩模的干蚀刻技术，在半导体晶片的预定区域中形成沟槽。 具体地说，在切割线附近的区域形成沟槽。

公开(公告)号：US08106518B2

公开(公告)日：2012-01-31

申请号：US12640766

申请日：2009-12-17

申请人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

发明人： Michihiro Kawashita ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

CPC分类号： H01L25/0657 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L25/074 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16058 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/274 ,  H01L2224/81136 ,  H01L2224/81345 ,  H01L2224/81365 ,  H01L2224/81801 ,  H01L2224/81898 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1205 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1451 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.

摘要翻译： 在层叠多个半导体芯片的半导体装置中，不会降低生产率而提高性能。 半导体器件具有多个元件，层间绝缘膜，焊盘和与依次形成在硅基板的主表面上的焊盘电连接的凸块电极，并且具有形成在硅衬底的背面上的背面电极 硅基板并与凸块电极电连接。 凸块电极具有贯穿焊盘并朝向硅衬底侧突出的突出部分。 背面电极形成为从硅衬底的背面侧朝向主面侧到达突起电极的突出部，并覆盖未到达的背面电极孔部的内部 垫，使得背面电极与凸块电极电连接。

公开(公告)号：US20090212437A1

公开(公告)日：2009-08-27

申请号：US12389071

申请日：2009-02-19

申请人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

发明人： Yukihiro Kumagai ,  Hiroyuki Ohta ,  Naotaka Tanaka ,  Masahiko Fujisawa ,  Akihiko Ohsaki

IPC分类号： H01L23/532

CPC分类号： H01L23/53238 ,  H01L23/3128 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/0401

摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.

摘要翻译： 在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。 在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触 形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

公开(公告)号：US20090014843A1

公开(公告)日：2009-01-15

申请号：US12133828

申请日：2008-06-05

申请人： Michihiro KAWASHITA ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

发明人： Michihiro KAWASHITA ,  Yasuhiro Yoshimura ,  Naotaka Tanaka ,  Takahiro Naito ,  Takashi Akazawa

IPC分类号： H01L23/52 ,  H01L21/60 ,  H01L21/4763

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L24/05 ,  H01L24/90 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05553 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/90 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.

摘要翻译： 形成从半导体衬底的第二表面到达焊盘的通硅。 贯穿硅通孔中的穿透空间由直径小于第一孔直径的第一孔和第二孔形成。 第一孔由半导体衬底的第二表面到层间绝缘膜的中间形成。 此外，形成从第一孔的底部到达垫的第二孔。 然后，形成在半导体衬底的第一表面上的层间绝缘膜具有反映第一孔的底表面和半导体衬底的第一表面之间的台阶差的台阶形状。 更具体地说，第一孔的底表面和垫之间的层间绝缘膜的厚度小于其它部分的厚度。

公开(公告)号：US20070187823A1

公开(公告)日：2007-08-16

申请号：US11783983

申请日：2007-04-13

申请人： Naotaka Tanaka ,  Tomio Iwasaki ,  Hideo Miura ,  Yasuyuki Nakajima ,  Tomoo Matsuzawa

发明人： Naotaka Tanaka ,  Tomio Iwasaki ,  Hideo Miura ,  Yasuyuki Nakajima ,  Tomoo Matsuzawa

IPC分类号： H01L23/48

CPC分类号： H01L23/53238 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48453 ,  H01L2224/48465 ,  H01L2224/4851 ,  H01L2224/48624 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85205 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/20751 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00015

摘要： An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.

摘要翻译： 本发明的目的在于，对于具有Cu互连/ Low-k材料的堆叠互连结构的LSI，可以实现能够减少对焊盘的损伤的窄间距引线接合技术和类似于传统LSI的 铝互连。 在具有由Cu互连/ Low-k电介质材料制成的多层互连的半导体器件中，上述目的可以通过一种焊盘结构来实现，其中所有的布线层直到最上盖互连件都是由Cu 布线层和由Cu层形成的接合焊盘部分在Cu层上装有诸如Ti（钛）膜（钨）的耐火材料中间金属层和中间金属层上的铝合金层。

公开(公告)号：US20070176298A1

公开(公告)日：2007-08-02

申请号：US11652235

申请日：2007-01-10

申请人： Yasuo Osone ,  Kenya Kawano ,  Chiko Yorita ,  Yu Hasegawa ,  Yuji Shirai ,  Naotaka Tanaka ,  Seiichi Tomoi ,  Hiroshi Okabe

发明人： Yasuo Osone ,  Kenya Kawano ,  Chiko Yorita ,  Yu Hasegawa ,  Yuji Shirai ,  Naotaka Tanaka ,  Seiichi Tomoi ,  Hiroshi Okabe

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/3677 ,  H01L23/3121 ,  H01L23/34 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2223/6644 ,  H01L2223/6688 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/48237 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.

摘要翻译： 发热时刻不同的加热元件层叠在堆叠状态，允许靠近布线基板的加热元件用作另一个加热元件的热​​扩散板。

公开(公告)号：US20070018320A1

公开(公告)日：2007-01-25

申请号：US11518889

申请日：2006-09-12

申请人： Kazumasa Tanida ,  Yoshihiko Nemoto ,  Naotaka Tanaka

发明人： Kazumasa Tanida ,  Yoshihiko Nemoto ,  Naotaka Tanaka

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/11 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099

摘要： A semiconductor chip production method including the steps of: forming a front side recess in a semiconductor substrate; depositing a metal material in the front side recess to form a front side electrode electrically connected to a functional device formed on the front surface; removing a rear surface portion of the semiconductor substrate to reduce the thickness of the semiconductor substrate to a thickness greater than the depth of the front side recess; forming a rear side recess communicating with the front side recess in the rear surface of the semiconductor substrate after the thickness reducing step; and depositing a metal material in the rear side recess to form a rear side electrode electrically connected to the front side electrode for formation of a through-electrode.

摘要翻译： 一种半导体芯片制造方法，包括以下步骤：在半导体衬底中形成前侧凹部; 在所述前侧凹部中沉积金属材料，以形成与形成在所述前表面上的功能元件电连接的前侧电极; 去除半导体衬底的后表面部分以将半导体衬底的厚度减小到大于前侧凹槽的深度的厚度; 在所述厚度减小步骤之后形成与所述半导体衬底的后表面中的所述前侧凹部连通的后侧凹部; 以及在后侧凹部中沉积金属材料，以形成与前侧电极电连接以形成贯通电极的后侧电极。

公开(公告)号：US20050029673A1

公开(公告)日：2005-02-10

申请号：US10941570

申请日：2004-09-14

申请人： Yasuhiro Naka ,  Naotaka Tanaka ,  Ikuo Yoshida ,  Satoshi Imasu ,  Takahiro Naito

发明人： Yasuhiro Naka ,  Naotaka Tanaka ,  Ikuo Yoshida ,  Satoshi Imasu ,  Takahiro Naito

IPC分类号： H01L25/10 ,  H01L21/304 ,  H01L21/56 ,  H01L23/12 ,  H01L23/36 ,  H01L23/538 ,  H01L23/552 ,  H01L25/18 ,  H01L23/52

CPC分类号： H01L23/538 ,  H01L21/563 ,  H01L23/36 ,  H01L23/552 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/0401

摘要： In a multi-chip-module type semiconductor device, first and second semiconductor elements, a main component of each of the semiconductor elements being semiconductor material to form a semiconductor electric circuit in each of the semiconductor elements, are mounted on and electrically connected to a substrate adapted to be mounted onto a mother board and to be electrically connected to the mother board so that the each of the semiconductor elements is electrically connected to the mother board through the substrate.

摘要翻译： 在多芯片模块型半导体器件中，第一和第二半导体元件，每个半导体元件的主要部件是半导体材料，用于在每个半导体元件中形成半导体电路，安装在电连接到 衬底，其适于安装在母板上并与母板电连接，使得每个半导体元件通过衬底电连接到母板。

公开(公告)号：US06844219B2

公开(公告)日：2005-01-18

申请号：US10136409

申请日：2002-05-02

申请人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

发明人： Makoto Kitano ,  Akihiro Yaguchi ,  Naotaka Tanaka ,  Takeshi Terasaki ,  Ichiro Anjoh ,  Ryo Haruta ,  Asao Nishimura ,  Junichi Saeki

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/00 ,  H01L23/02 ,  H01L23/16 ,  H01L23/31 ,  H01L23/488 ,  H01L23/495 ,  H01L23/498 ,  H05K3/34 ,  H01L21/44

CPC分类号： H01L23/16 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/05554 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K3/3426 ,  H05K3/3436 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

摘要翻译： 可以提高焊料凸块的连接可靠性和制造生产率的半导体器件。 在其表面具有布线图案的绝缘带被粘合到引线框架上。 半导体元件被加载并且电路形成的表面和半导体元件的侧面被密封树脂​​密封。 在形成各个半导体器件的布置之后，将引线框架分离成单独的金属板以形成单独的半导体器件。 这种同时生产多个半导体器件提高了生产率，并且提高了绝缘带的平坦度，从而提高了焊料凸块的连接可靠性。