摘要:
A method of fabricating a semiconductor-on-diamond composite substrate, the method comprising: (i) starting with a native semiconductor wafer comprising a native silicon carbidesubstrate on which a compound semiconductor is disposed; (ii) bonding a silicon carbide carrier substrate to the compound semiconductor; (iii) removing the native silicon carbide substrate; (iv) forming a nucleation layer over the compound semiconductor; (v) growing polycrystalline chemical vapour deposited (CVD) diamond on the nucleation layer to form a composite diamond-compound semiconductor-silicon carbide wafer, and (vi) removing the silicon carbide carrier substrate y laser lift-off to achieve a layered structure comprising the compound semiconductor bonded to the polycrystalline CVD diamond via the nucleation layer, wherein in step (ii) the silicon carbide carrier substrate is bonded to the compound semiconductor via a laser absorption material which absorbs laser light, wherein the laser has a coherence length shorter than a thickness of the silicon carbide carrier substrate.
摘要:
A packaged semiconductor chip includes a power amplifier die including a semiconductor substrate, and an input contact pad, an output contact pad, first and second direct-current (DC) contact pads, one or more transistors having an input coupled to the input contact pad, and an input bias coupling path electrically coupling the first DC contact pad to the second DC contact pad and the input contact pad implemented on the semiconductor substrate. The chip further includes a lead frame having one or more radio-frequency input pins electrically coupled to the input contact pad, one or more radio-frequency output pins electrically coupled to the output contact pad, and first and second input bias pins electrically coupled to the first and second DC contact pads, respectively.
摘要:
An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through- hole structure forming at least one conductive pathway through a thickness of the insulating core, A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.
摘要:
In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.
摘要:
Die Erfindung betrifft ein Verfahren zum Aufbringen einer aus einer Grundschicht und einer Schutzschicht bestehenden Bondschicht auf ein Substrat mit folgenden Verfahrensschritten: Aufbringen eines oxidierbaren Grundmaterials als Grundschicht auf eine Bondseite des Substrats, zumindest teilweises Bedecken der Grundschicht mit einem in dem Grundmaterial zumindest teilweise lösbaren Schutzmaterial als Schutzschicht. Weiterhin betrifft die Erfindung ein korrespondierendes Substrat.
摘要:
In accordance with certain embodiments, a semiconductor die is adhered directly to a yielding substrate with a pressure-activated adhesive notwithstanding any nonplanarity of the surface of the semiconductor die or non-coplanarity of the semiconductor die contacts.
摘要:
Die Erfindung betrifft ein Verfahren zum Bonden einer ersten Fläche (1a) und einer zweiten Fläche (7a) mittels einer Zwischenschicht (3), umfassend die Schritte: a) Bereitstellen eines ersten Gegenstandes (1) mit der ersten Fläche (1a), b) Bereitstellen von fließfähigem, verfestigbarem Material für die Zwischenschicht (3), c) Bereitstellen eines zweiten Gegenstandes (7) mit der zweiten Fläche (7a), d) Auftragen des Materials für die Zwischenschicht auf die erste Fläche (1a), so dass eine die Fläche umlaufende Aufwölbung (3a) entsteht, e) Anlegen eines Vakuums um den ersten Gegenstand (1) und den zweiten Gegenstand (2), f) Kontaktieren der zweiten Fläche (7a) des zweiten Gegenstandes (7) mit der umlaufenden Aufwölbung, so dass ein abgeschlossener Hohlraum (5) entsteht, g) Erhöhen des Umgebungsdruckes, so dass der Hohlraum (5) aufgehoben wird, ohne dass es zu einem Gaseinstrom in ihn kommt und h) Erhöhen der Viskosität des Materials für die Zwischenschicht.
摘要:
A III-N enhancement-mode transistor includes a III-N structure including a conductive channel, source and drain contacts, and a gate electrode between the source and drain contacts. An insulator layer is over the III-N structure, with a recess formed through the insulator layer in a gate region of the transistor, with the gate electrode at least partially in the recess. The transistor further includes a field plate having a portion between the gate electrode and the drain contact, the field plate being electrically connected to the source contact. The gate electrode includes an extending portion that is outside the recess and extends towards the drain contact. The separation between the conductive channel and the extending portion of the gate electrode is greater than the separation between the conductive channel and the portion of the field plate that is between the gate electrode and the drain contact.