摘要:
A lead-free, antimony-free solder alloy comprising: (a) from 1 to 4 wt.% silver (b) from 0.5 to 6 wt.% bismuth (c) from 3.55 to 15 wt.% indium (d) 3 wt.% or less of copper (e) optionally one or more of the following elements 0 to 1 wt.% nickel 0 to 1 wt.% of titanium 0 to 1 wt.% manganese 0 to 1 wt.% of rare earths, such as cerium 0 to 1 wt.% of chromium 0 to 1 wt.% germanium 0 to 1 wt.% of gallium 0 to 1 wt.% of cobalt 0 to 1 wt.% of iron 0 to 1 wt.% of aluminum 0 to 1 wt.% of phosphorus 0 to 1 wt.% of gold 0 to 1 wt.% of tellurium 0 to 1 wt.% of selenium 0 to 1 wt.% of calcium 0 to 1 wt.% of vanadium 0 to 1 wt.% of molybdenum 0 to 1 wt.% of platinum 0 to 1 wt.% of magnesium (f) the balance tin, together with any unavoidable impurities.
摘要:
The connection arrangement (100, 200, 300, 400) comprises at least one electric and/or electronic component (1). The at least one electric and/or electronic component (10) has at least one connection face (11), which is connected in a bonded manner to a join partner (40) by means of a connection layer (20). The connection layer (20) can for example be an adhesive, soldered, welded, sintered connection or another known connection that connects joining partners while forming a material connection. Furthermore, a reinforcement layer (30') is arranged adjacent to the connection layer (20) in a bonded manner. The reinforcement layer (30') has a higher modulus of elasticity than the connection layer (20). A particularly good protective effect is achieved if the reinforcement layer (30') is formed in a frame-like manner by an outer and an inner boundary (36, 35) and, at least with the outer boundary (36) thereof, encloses the connection face (11) of the at least one electric and/or electronic component (10).
摘要:
Alloy compositions and techniques for reducing IMC thickness and oxidation of metals and alloys are disclosed. In one particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy or mixture consisting essentially of from about 90% to about 99.999% by weight indium and from about 0.001% to about 10% by weight germanium and unavoidable impurities. In another particular exemplary embodiment, the alloy compositions may be realized as a composition of alloy consisting essentially of from about 90% to about 99.999% by weight gallium and from about 0.001% to about 10% by weight germanium and unavoidable impurities.
摘要:
A microelectronic assembly (10, 110, 210, 310, 410) includes a first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) having a first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a second substrate (14, 114, 214, 314, 414) having a second conductive element (26, 126, 226, 326, 426). The assembly further includes an electrically conductive alloy mass (16, 116) joined to the first and second conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022), including a first, a second and a third material. First and second materials of the alloy mass (16, 116) each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) to a relatively lower amount toward the second conductive element (26, 126, 226, 326, 426), and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element (26, 126, 226, 326, 426) to a relatively lower amount toward the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022). The microelectronic assembly (10, 110, 210, 310, 410) is formed by aligning the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912), having a first bond component (30, 230, 330, 430), with the second substrate (14, 114, 214, 314, 414), having a second bond component (40, 240, 340, 440), such that the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components are in contact with each other, the first bond component (30, 230, 330, 430, 1030) including a first material layer (36, 536, 636, 736, 836, 936) adjacent the first conductive element (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) and a first protective layer (38, 538, 638, 738, 838, 938) overlying the first material layer (36, 536, 636, 736, 836, 936), the second bond component (40, 240, 340, 440) including a second material layer (46) adjacent the second conductive element (26) and a second protective layer (48) overlying the second material layer (46), and heating the first (30, 230, 330, 430, 1030) and second (40, 240, 340, 440) bond components such that at least portions of the first (36, 536, 636, 736, 836, 936) and second (46) material layers diffuse together to form the alloy mass (16, 116) joining the first (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and second (14, 114, 214, 314, 414) substrates with one another. There may be formed a plurality of first conductive elements (26, 126, 226, 326, 426, 526, 626, 726, 826, 926, 1022) on the first substrate (12, 112, 212, 312, 412, 512, 612, 712, 812, 912) and a plurality of second conductive elements (26, 126, 226, 326, 426) on the second substrate (14, 114, 214, 314, 414), joined by a plurality of conductive alloy masses (16, 116). The conductive alloy mass (116) may also surround and hermetically seal an internal volume.
摘要:
A dual solder layer for fluidic self assembly, an electrical component substrate, and method employing same is described. The dual solder layer comprises a layer of a self-assembly solder (12) disposed on a layer of a base solder (14) which is disposed on the solder pad (16) of an electrical component substrate(18). The self-assembly solder (12) has a liquidus temperature less than a first temperature and the base solder (14) has a solidus temperature greater than the first temperature. The self-assembly solder (12) liquefies at the first temperature during a fluidic self assembly method to cause electrical components (10) to adhere to the substrate (18). After attachment, the substrate(18) is removed from the bath (20) and heated so that the base solder (14) and self-assembly solder (12) combine to form a composite alloy (22) which forms the final electrical solder connection between the component (10) and the solder pad (16) on the substrate (18).
摘要:
Various methods and apparatus for establishing thermal pathways for a semiconductor device are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip (20) that has a substrate and a first active circuitry portion (40) extending a first distance into the substrate. A barrier (135) is formed in the first semiconductor chip (20) that surrounds but is laterally separated from the first active circuitry portion (40) and extends into the substrate a second distance greater than the first distance.
摘要:
A lead-free, antimony-free solder alloy comprising: (a) from 1 to 4 wt.% silver (b) from 0.5 to 6 wt.% bismuth (c) from 3.55 to 15 wt.% indium (d) 3 wt.% or less of copper (e) optionally one or more of the following elements 0 to 1 wt.% nickel 0 to 1 wt.% of titanium 0 to 1 wt.% manganese 0 to 1 wt.% of rare earths, such as cerium 0 to 1 wt.% of chromium 0 to 1 wt.% germanium 0 to 1 wt.% of gallium 0 to 1 wt.% of cobalt 0 to 1 wt.% of iron 0 to 1 wt.% of aluminum 0 to 1 wt.% of phosphorus 0 to 1 wt.% of gold 0 to 1 wt.% of tellurium 0 to 1 wt.% of selenium 0 to 1 wt.% of calcium 0 to 1 wt.% of vanadium 0 to 1 wt.% of molybdenum 0 to 1 wt.% of platinum 0 to 1 wt.% of magnesium (f) the balance tin, together with any unavoidable impurities.
摘要:
Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate.
摘要:
Various methods and apparatus for establishing thermal pathways for a semiconductor device using solder-type thermal material (90) are disclosed. In one aspect, a method of manufacturing is provided that includes providing a first semiconductor chip (20) that has a substrate and a first active circuitry portion (40) extending a first distance into the substrate. A barrier (135),which inhibits the diffusion of solder, is formed in the first semiconductor chip (20) that surrounds but is laterally separated from the first active circuitry portion (40) and extends into the substrate a second distance greater than the first distance.
摘要:
A composition comprising at least one liquid metal having a melting point less than 35°C; at least one electrically insulating solid filler comprising thermally conducting materials; at least one resin is provided. The composition is both thermally conducting and electrically insulating and has utility in the preparation of electronic devices comprising heat generating and heat dissipating structures. In one instance a composition is provided which comprises a liquid metal selected from the group consisting of gallium, gallium alloys, and mixtures thereof, a boron nitride particulate filler, and a silicone resin, wherein said liquid metal and particulate filler are present in a volume ratio of about 1:0.4 to about 1: 10. A method of making and using such a composition is also provided.