公开(公告)号：US12131796B2

公开(公告)日：2024-10-29

申请号：US18195860

申请日：2023-05-10

申请人： Rambus Inc.

发明人： Yohan Frans

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  H01L25/065

CPC分类号： G11C7/10 ,  G11C5/02 ,  G11C5/063 ,  G11C7/22 ,  G11C5/025 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/4824 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311

摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.

公开(公告)号：US20240257863A1

公开(公告)日：2024-08-01

申请号：US18584371

申请日：2024-02-22

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas A. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC分类号： G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC分类号： G11C11/4093 ,  G11C5/025 ,  G11C5/063 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C29/824 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  G11C7/10 ,  G11C7/1012 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/12 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181

摘要： A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US20240047331A1

公开(公告)日：2024-02-08

申请号：US17879125

申请日：2022-08-02

申请人： NANYA TECHNOLOGY CORPORATION

发明人： WU-DER YANG

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/13 ,  H01L21/48

CPC分类号： H01L23/49833 ,  H01L24/48 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/13 ,  H01L24/73 ,  H01L24/32 ,  H01L24/33 ,  H01L21/4853 ,  H01L2924/15311 ,  H01L2224/73215 ,  H01L2224/4824 ,  H01L2924/15151 ,  H01L2924/182 ,  H01L2224/3201 ,  H01L2224/32225 ,  H01L2224/32058 ,  H01L2224/3303 ,  H01L2224/33055 ,  H01L2224/48464

摘要： A WBGA package and a method of manufacturing a WBGA package are provided. The WBGA package includes a first substrate having a first through hole and a second substrate having a second through hole over the first through hole of the first substrate. The WBGA package also includes an electronic component having an active surface over the second through hole of the second substrate.

公开(公告)号：US11830845B2

公开(公告)日：2023-11-28

申请号：US17867554

申请日：2022-07-18

申请人： Adeia Semiconductor Solutions LLC

发明人： Hiroaki Sato ,  Teck-Gyu Kang ,  Belgacem Haba ,  Philip R. Osborn ,  Wei-Shun Wang ,  Ellis Chau ,  Ilyas Mohammed ,  Norihito Masuda ,  Kazuo Sakuma ,  Kiyoaki Hashimoto ,  Kurosawa Inetaro ,  Tomoyuki Kikuchi

IPC分类号： H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L25/04 ,  H01L27/146 ,  H01L21/56 ,  H01L23/538

CPC分类号： H01L24/18 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49811 ,  H01L24/73 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L27/14618 ,  H01L27/14625 ,  H01L21/56 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1713 ,  H01L2224/17179 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4824 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48455 ,  H01L2224/48464 ,  H01L2224/49105 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/107 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01049 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/19107

摘要： Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

公开(公告)号：US20230245984A1

公开(公告)日：2023-08-03

申请号：US18128044

申请日：2023-03-29

申请人： STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

发明人： Denis FARISON ,  Romain COFFY ,  Jean-Michel RIVIERE

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/528 ,  H01L25/065

CPC分类号： H01L23/576 ,  H01L21/563 ,  H01L23/528 ,  H01L24/09 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49112 ,  H01L2225/06555 ,  H01L2924/14 ,  H04L9/002

摘要： A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.

公开(公告)号：US20190088565A1

公开(公告)日：2019-03-21

申请号：US16196262

申请日：2018-11-20

申请人： Micron Technology, Inc.

发明人： Chan Yoo ,  Akshay Singh ,  Yi Xu ,  Liana Foster ,  Steven Eskildsen

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

CPC分类号： H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45169 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3862 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor die that includes a first die located on a first side of an interposer and a second die located on a second side of the interposer. Active sides of the first and second dies may each face the interposer. A bond wire may electrically connect the first die to the second side of the interposer and a bond wire may electrically connect the second die to the first side of the interposer. The bond wires may extend through a plurality of windows in the interposer. First and second dies may be attached to a first side of an interposer and may be electrically connected to a second side of the interposer through windows and third and fourth dies may be attached to a second side of the interposer and may be electrically connected to the first side of the interposer through windows.

公开(公告)号：US20180331074A1

公开(公告)日：2018-11-15

申请号：US16037453

申请日：2018-07-17

申请人： Invensas Corporation

发明人： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC分类号： H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  G11C5/04 ,  H01L23/48

CPC分类号： H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85

摘要： A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

公开(公告)号：US10083903B1

公开(公告)日：2018-09-25

申请号：US15201575

申请日：2016-07-04

申请人： STATS ChipPAC Pte. Ltd.

发明人： In Sang Yoon ,  DeokKyung Yang ,  Sungmin Song

IPC分类号： H01L23/52 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A method of manufacture of an integrated packaging system includes: providing a substrate; mounting an integrated circuit on the substrate; mounting an interposer substrate having an interposer pad on the integrated circuit; covering an encapsulant over the integrated circuit and the interposer substrate; forming a hole through the encapsulant aligned over the interposer pad; and placing a conductive connector on and in direct contact with the interposer pad.

公开(公告)号：US20180211896A1

公开(公告)日：2018-07-26

申请号：US15936715

申请日：2018-03-27

申请人： Micron Technology, Inc.

发明人： Matt E. Schwab ,  J. Michael Brooks ,  David J. Corisis

IPC分类号： H01L23/31 ,  H01L23/16 ,  H01L23/492 ,  H01L23/00 ,  H01L25/065 ,  H01L23/36

CPC分类号： H01L23/3128 ,  H01L23/16 ,  H01L23/36 ,  H01L23/4924 ,  H01L24/06 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.

公开(公告)号：US10007622B2

公开(公告)日：2018-06-26

申请号：US15481288

申请日：2017-04-06

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen

IPC分类号： G06F13/16 ,  G11C8/12 ,  G06F12/06 ,  G11C5/06 ,  G11C8/06 ,  G11C5/04

CPC分类号： G06F13/1673 ,  G06F12/00 ,  G06F12/0623 ,  G06F13/1694 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L2224/4824 ,  H01L2924/15311

摘要： A method for reducing load in a memory module. In such a method, a plurality of memory chips are coupled to a circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.