公开(公告)号：US09905531B2

公开(公告)日：2018-02-27

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/18 ,  H01L21/306 ,  H01L21/66

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

公开(公告)号：US20150235890A1

公开(公告)日：2015-08-20

申请号：US14182689

申请日：2014-02-18

Applicant: Infineon Technologies AG

Inventor： Bernhard Goller ,  Eva-Maria Hess ,  Edward Fuergut ,  Christian Schweiger

IPC: H01L21/683 ,  H01L21/268 ,  H01L21/762 ,  H01L23/00 ,  H01L21/78 ,  H01L21/304

CPC classification number: H01L21/6835 ,  H01L21/268 ,  H01L21/304 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76251 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/02 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0231 ,  H01L2224/04105 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/82106 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/00 ,  H01L2224/82 ,  H05K3/467 ,  H01L2224/03 ,  H01L2924/01029

Abstract: A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.

Abstract translation: 一种制造半导体器件的方法包括提供具有第一侧和与第一侧相对的第二侧的载流子和半导体晶片。 该方法包括将介电材料施加到载体或半导体晶片，并通过电介质材料将半导体晶片接合到载体上。 该方法包括处理半导体晶片并从半导体晶片去除载体，使得介电材料保留在半导体晶片上，以提供包括电介质材料的半导体器件。

公开(公告)号：US09018664B2

公开(公告)日：2015-04-28

申请号：US14144111

申请日：2013-12-30

Applicant: Nichia Corporation

Inventor： Masafumi Kuramoto ,  Satoru Ogawa ,  Miki Niwa

IPC: H01L33/62 ,  H01L33/44 ,  H01L23/00 ,  H01L23/08 ,  H01L23/29 ,  H01L23/495 ,  H01S5/022

CPC classification number: H01L33/44 ,  H01L23/08 ,  H01L23/293 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/83 ,  H01L33/62 ,  H01L2224/05568 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/2712 ,  H01L2224/2745 ,  H01L2224/275 ,  H01L2224/29023 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29187 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83055 ,  H01L2224/83075 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83487 ,  H01L2224/8383 ,  H01L2224/8384 ,  H01L2224/83894 ,  H01L2224/83895 ,  H01L2224/83896 ,  H01L2224/83907 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01063 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/0541 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/201 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/3025 ,  H01L2933/0066 ,  H01S5/0226 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/48 ,  H01L2224/05599

Abstract: An object of the invention is to provide a method for producing a conductive member having low electrical resistance, and the conductive member is obtained using a low-cost stable conductive material composition that does not contain an adhesive. A method for producing a semiconductor device in which silver or silver oxide provided on a surface of a base and silver or silver oxide provided on a surface of a semiconductor element are bonded, includes the steps of arranging a semiconductor element on a base such that silver or silver oxide provided on a surface of the semiconductor element is in contact with silver or silver oxide provided on a surface of the base, temporarily bonding the semiconductor element and the base by applying a pressure or an ultrasonic vibration to the semiconductor element or the base, and permanently bonding the semiconductor element and the base by applying heat having a temperature of 150 to 900° C. to the semiconductor device and the base.

Abstract translation: 本发明的目的是提供一种用于制造具有低电阻的导电构件的方法，并且使用不含粘合剂的低成本稳定的导电材料组合物获得导电构件。 一种制造半导体器件的方法，其中设置在基底表面上的银或氧化银和设置在半导体元件的表面上的银或银氧化物结合，包括以下步骤：将半导体元件布置在基底上，使得银 或设置在半导体元件的表面上的氧化银与设置在基板的表面上的银或氧化银接触，通过向半导体元件或基底施加压力或超声波振动来临时接合半导体元件和基座 并且通过向半导体器件和基底施加温度为150至900℃的热而将半导体元件和基底永久地接合。

公开(公告)号：US09917067B1

公开(公告)日：2018-03-13

申请号：US15419280

申请日：2017-01-30

Applicant: KULITE SEMICONDUCTOR PRODUCTS, INC.

Inventor： Sorin Stefanescu

IPC: H01L23/06 ,  H01L23/02 ,  H01L23/48 ,  H01L21/44 ,  H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0508 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/45144 ,  H01L2224/45169 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/351 ,  H01L2924/365

Abstract: Systems and methods are disclosed for providing an interconnection for extending high-temperature use in sensors and other electronic devices. The interconnection includes a semiconductor layer; an ohmic contact layer disposed on a first region of the semiconductor layer; an insulating layer disposed on a second region of the semiconductor layer, where the second region differs from the first region; a metal layer disposed above at least the insulating layer and the ohmic contact layer; and a connecting conductive region disposed on the metal layer and in vertical alignment with a third region of the semiconductor layer. The third region differs from the first region and is offset from the ohmic contact layer at the first region. The offset is configured to extend an operational lifetime of the interconnection apparatus, particularly when the interconnection apparatus is exposed to high temperature environments.

公开(公告)号：US20150380333A1

公开(公告)日：2015-12-31

申请号：US14827142

申请日：2015-08-14

Applicant: Semtech Corporation

Inventor： Victor Hugo Cruz ,  David Francis Courtney

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/291 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/34 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05639 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/37184 ,  H01L2224/37639 ,  H01L2224/37655 ,  H01L2224/40247 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/48247 ,  H01L2224/4847 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48755 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/097 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/17738 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/201 ,  H01L2924/20111 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: A high temperature, non-cavity package for non-axial electronics is designed using a glass ceramic compound with that is capable of being assembled and operating continuously at temperatures greater that 300-400° C. Metal brazes, such as silver, silver colloid or copper, are used to connect the semiconductor die, lead frame and connectors. The components are also thermally matched such that the packages can be assembled and operating continuously at high temperatures and withstand extreme temperature variations without the bonds failing or the package cracking due to a thermal mismatch.

Abstract translation: 用于非轴向电子器件的高温非空腔封装是使用玻璃陶瓷化合物设计的，其能够在高于300-400℃的温度下连续组装和操作。金属钎焊，例如银，银胶体或 铜，用于连接半导体管芯，引线框架和连接器。 这些部件也是热匹配的，使得封装可以在高温下连续地组装和操作，并且可承受极端的温度变化，而不会发生键失效或者由于热失配引起的封装破裂。

公开(公告)号：US20150206847A1

公开(公告)日：2015-07-23

申请号：US14453969

申请日：2014-08-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Hae Cheon KIM ,  Ho Kyun AHN ,  Byoung Gue MIN ,  Hyung Sup YOON ,  Jong Won LIM

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/48 ,  H01L2224/0225 ,  H01L2224/03466 ,  H01L2224/03848 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1033 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1423 ,  H01L2924/201 ,  H01L2924/37001 ,  H01L2224/45099

Abstract: The present invention relates to a GaN transistor, and a method of fabricating the same, in which a structure of a bonding pad is improved by forming an ohmic metal layer at edges of the bonding pad of a source, a drain, and a gate so as to be appropriate to wire-bonding or a back-side via-hole forming process. Accordingly, adhesive force between a metal layer of the bonding pad and a GaN substrate is enhanced by forming the ohmic metal at the edges of the bonding pad during manufacturing of the GaN transistor, thereby minimizing a separation phenomenon of a pad layer during the wire-bonding or back-side via-hole forming process, and improving reliability of a device.

Abstract translation: 本发明涉及一种GaN晶体管及其制造方法，其中通过在源极，漏极和栅极的焊盘的边缘处形成欧姆金属层来改善焊盘的结构，因此 适于引线接合或背面通孔形成工艺。 因此，通过在制造GaN晶体管期间在焊盘的边缘处形成欧姆金属，可以增强焊盘的金属层与GaN基板之间的粘合力， 接合或背面通孔形成工艺，并提高器件的可靠性。

公开(公告)号：US20150123263A1

公开(公告)日：2015-05-07

申请号：US14400121

申请日：2013-04-02

Applicant: Robert Bosch GmbH

Inventor： Christiane Frueh ,  Michael Guenther ,  Thomas Herboth

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/2731 ,  H01L2224/2732 ,  H01L2224/27442 ,  H01L2224/27505 ,  H01L2224/27901 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/75315 ,  H01L2224/831 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83208 ,  H01L2224/8384 ,  H01L2924/01047 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/201 ,  H01L2924/20101 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/00

Abstract: The invention relates to a method for joining a semiconductor (20) to a substrate (10), comprising the following steps: •applying a first paste layer (1) of a sintering paste to the substrate; •heating and compressing the first paste layer to form a first sintered layer; •applying a second paste layer (2) of a sintering paste to the first sintered layer and arranging a semiconductor (20) on the second paste layer; •heating and compressing the second paste layer (2) to form a second sintered layer. The invention further relates to a semiconductor component produced by means of the method.

Abstract translation: 本发明涉及将半导体（20）接合到基板（10）的方法，包括以下步骤：将烧结糊的第一糊剂层（1）施加到基底上; 加热和压缩第一浆料层以形成第一烧结层; 将烧结膏的第二浆料层（2）施加到所述第一烧结层并将半导体（20）布置在所述第二糊料层上; 加热和压缩第二浆料层（2）以形成第二烧结层。 本发明还涉及通过该方法制造的半导体部件。

公开(公告)号：US09536854B2

公开(公告)日：2017-01-03

申请号：US14893833

申请日：2015-03-31

Applicant: Nippon Micrometal Corporation ,  Nippon Steel & Sumikin Materials Co., Ltd.

Inventor： Takashi Yamada ,  Daizo Oda ,  Ryo Oishi ,  Teruo Haibara ,  Tomohiro Uno

IPC: H01B5/00 ,  H01L23/00 ,  B21C1/00 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  B23K35/30 ,  B23K35/02

CPC classification number: H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  B23K35/0227 ,  B23K35/3006 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/45012 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/00015 ,  H01L2924/01201

Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 在线中心横截面的方向上，相对于线纵向的角度差为15°以下的晶体方向<100>的面积比为50％〜90％，（3）当 在线表面测定线长方向的晶体方向，晶体方向<100>与线长度方向的角度差为15°以下的面积比为50％〜90％。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。

公开(公告)号：US20160204078A1

公开(公告)日：2016-07-14

申请号：US14596861

申请日：2015-01-14

Applicant: International Business Machines Corporation

Inventor： Stephen W. Bedell ,  Cheng-Wei Cheng ,  Keith E. Fogel ,  Ning Li ,  Devendra K. Sadana

IPC: H01L23/00 ,  B32B37/14 ,  B32B38/10

CPC classification number: H01L24/83 ,  B32B37/28 ,  B32B2457/14 ,  H01L2224/83002 ,  H01L2224/83047 ,  H01L2224/83095 ,  H01L2224/83888 ,  H01L2924/01028 ,  H01L2924/201

Abstract: A first substrate including a radius of curvature and a stressor layer is first provided. An outermost bowed, e.g., curved, surface of the first substrate is then brought into intimate contact with a surface of a second substrate. Bonding of the entirety of the first substrate to the second substrate is then achieved by reducing the radius of curvature of the first substrate by controlling the temperature at which bonding occurs.

Abstract translation: 首先提供包括曲率半径和应力层的第一衬底。 然后使第一基底的最外面的弯曲的，例如弯曲的表面与第二基底的表面紧密接触。 然后通过控制发生接合的温度来减小第一衬底的整体的第二衬底的接合，从而减小第一衬底的曲率半径。

公开(公告)号：US20160111389A1

公开(公告)日：2016-04-21

申请号：US14893833

申请日：2015-03-31

Applicant: NIPPON MICROMETAL CORPORATION ,  NIPPON STEEL & SUMIKIN MATERIALS CO. LTD.

Inventor： Takashi YAMADA ,  Daizo ODA ,  Ryo OISHI ,  Teruo HAIBARA ,  Tomohiro UNO

IPC: H01L23/00 ,  C22C5/06 ,  C22F1/14 ,  C22C5/08

CPC classification number: H01L24/45 ,  B21C1/00 ,  B21C1/003 ,  B23K35/0227 ,  B23K35/3006 ,  C22C5/06 ,  C22C5/08 ,  C22F1/00 ,  C22F1/14 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/43848 ,  H01L2224/45012 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2924/00011 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/10253 ,  H01L2924/201 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2924/01049 ,  H01L2924/01045 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01016 ,  H01L2924/01017 ,  H01L2924/00015 ,  H01L2924/01201

Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 μm2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.5% or more is performed at least once. The final heat treatment temperature and the pre-final heat treatment temperature are made predetermined ranges.

Abstract translation: 用于半导体器件的接合线，其中通过（1）在包含线中心并且平行于线纵向（线中心横截面）的横截面中抑制倾斜故障和弹簧故障，不存在具有 长轴“a”的比率a / b和短轴“b”为10以上，面积为15μm2以上（“纤维织构”），（2）当测定线材纵向的晶体方向 在线中心横截面的方向上，相对于线纵向的角度差为15°以下的晶体方向<100>的面积比为50％〜90％，（3）当 在线表面测定线长方向的晶体方向，晶体方向<100>与线长度方向的角度差为15°以下的面积比为50％〜90％。 在拉伸步骤中，至少进行一次具有15.5％以上的面积减小率的拉拔操作。 将最终的热处理温度和预热处理温度设定为预定范围。