公开(公告)号：US08563418B2

公开(公告)日：2013-10-22

申请号：US13268091

申请日：2011-10-07

申请人： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

发明人： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC分类号： H01L21/44

CPC分类号： H01L24/49 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05013 ,  H01L2224/05553 ,  H01L2224/05556 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A method of making a semiconductor device includes providing a substrate, and forming a first conductive layer over the substrate. A patterned layer is formed over the first conductive layer. A second conductive layer is formed in the patterned layer. A height of the second conductive layer is greater than a height of the first conductive layer. The patterned layer is removed. A first bump and a second bump are formed over the first and second conductive layers, respectively, wherein the second bump overlaps the first bump, and wherein an uppermost surface of the second bump is vertically offset from an uppermost surface of the first bump. Bond wires are formed on the first and second bumps. The bond wires are arranged in a straight configuration. Lowermost surfaces of the first conductive layer and second conductive layer are substantially coplanar.

摘要翻译： 制造半导体器件的方法包括提供衬底，以及在衬底上形成第一导电层。 在第一导电层上形成图案层。 在图案化层中形成第二导电层。 第二导电层的高度大于第一导电层的高度。 去除图案层。 分别在第一和第二导电层上形成第一凸块和第二凸块，其中第二凸块与第一凸块重叠，并且其中第二凸块的最上表面垂直偏离第一凸块的最上表面。 接合线形成在第一和第二凸块上。 接合线布置成直线构型。 第一导电层和第二导电层的最下表面基本上共面。

公开(公告)号：US08525344B2

公开(公告)日：2013-09-03

申请号：US13034075

申请日：2011-02-24

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Dioscoro A. Merilo

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Dioscoro A. Merilo

IPC分类号： H01L29/40

CPC分类号： H01L21/76898 ,  H01L21/561 ,  H01L21/568 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02333 ,  H01L2224/02371 ,  H01L2224/03334 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/4848 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/81805

摘要： A semiconductor wafer has a plurality of semiconductor die with contact pads. An organic material is deposited in a peripheral region around the semiconductor die. A portion of the organic material is removed to form a plurality of vias. A conductive material is deposited in the vias to form conductive TOV. The conductive TOV can be recessed with respect to a surface of the semiconductor die. Bond wires are formed between the contact pads and conductive TOV. The bond wires can be bridged in multiple sections across the semiconductor die between the conductive TOV and contact pads. An insulating layer is formed over the bond wires and semiconductor die. The semiconductor wafer is singulated through the conductive TOV or organic material between the conductive TOV to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically connected through the bond wires and conductive TOV.

摘要翻译： 半导体晶片具有多个具有接触焊盘的半导体管芯。 有机材料沉积在半导体管芯周围的周边区域中。 去除部分有机材料以形成多个通孔。 导电材料沉积在通孔中以形成导电TOV。 导电TOV可以相对于半导体管芯的表面凹陷。 接合焊盘和导电TOV之间形成接合线。 接合线可跨接在导电TOV和接触焊盘之间的跨半导体管芯的多个部分中桥接。 在接合线和半导体管芯之上形成绝缘层。 半导体晶片通过导电TOV或有机材料在导电TOV之间分离，以分离半导体管芯。 多个半导体管芯可以通过接合线和导电TOV堆叠并电连接。

公开(公告)号：US08501544B2

公开(公告)日：2013-08-06

申请号：US13185384

申请日：2011-07-18

申请人： Reza A. Pagaila

发明人： Reza A. Pagaila

IPC分类号： H01L23/488 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a plurality of semiconductor die mounted to a carrier. An adhesive material is deposited over a portion of the semiconductor die and carrier to secure the semiconductor die to the carrier. The adhesive material is deposited over a side of the semiconductor die and over a surface of the carrier. The adhesive material can be deposited over a corner of the semiconductor die, or over a side of the semiconductor die, or around a perimeter of the semiconductor die. An encapsulant is deposited over the semiconductor die and carrier. The adhesive material reduces shifting of the semiconductor die with respect to the carrier during encapsulation. The adhesive material is cured and the carrier is removed. The adhesive material can also be removed. An interconnect structure is formed over the semiconductor die and encapsulant. The semiconductor die are singulated through the encapsulant and interconnect structure.

摘要翻译： 半导体器件具有安装到载体上的多个半导体管芯。 在半导体管芯和载体的一部分上沉积粘合剂材料以将半导体管芯固定到载体上。 粘合剂材料沉积在半导体管芯的一侧并且在载体的表面上。 粘合剂材料可以沉积在半导体管芯的角部上，或者在半导体管芯的一侧上，或者围绕半导体管芯的周边沉积。 密封剂沉积在半导体管芯和载体上。 粘合剂材料在封装期间减少了半导体管芯相对于载体的移动。 固化粘合剂材料并除去载体。 粘合剂材料也可以被去除。 在半导体管芯和密封剂上形成互连结构。 通过密封剂和互连结构将半导体裸片分离。

公开(公告)号：US08492201B2

公开(公告)日：2013-07-23

申请号：US12775324

申请日：2010-05-06

申请人： Reza A. Pagaila ,  Linda Pei Ee Chua ,  Byung Tai Do

发明人： Reza A. Pagaila ,  Linda Pei Ee Chua ,  Byung Tai Do

IPC分类号： H01L21/00

CPC分类号： H01L23/481 ,  H01L21/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

公开(公告)号：US08466544B2

公开(公告)日：2013-06-18

申请号：US13035669

申请日：2011-02-25

申请人： Reza A. Pagaila

发明人： Reza A. Pagaila

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L23/5384 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95121 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4647 ,  H05K2201/09518 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/03

摘要： A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

摘要翻译： 半导体器件具有在衬底上形成多个导电通孔和导电层的衬底。 半导体管芯安装在载体上。 衬底被安装到与载体相对的半导体管芯上。 在半导体管芯周围的衬底和载体之间沉积密封剂。 通过衬底和密封剂形成多个导电TMV。 导电TMV从密封剂突出以帮助互连结构的对准。 导电TMV电连接到导电层和导电通孔。 移除载体并且在与衬底相对的密封剂和半导体管芯的表面上形成互连结构。 互连结构电连接到导电TMV。 多个半导体器件可以通过衬底层叠并电连接，导电TMV和互连结构。

公开(公告)号：US08409978B2

公开(公告)日：2013-04-02

申请号：US12822504

申请日：2010-06-24

申请人： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

发明人： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC分类号： H01L21/44

CPC分类号： H01L23/4952 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

摘要翻译： 半导体器件具有垂直偏移的BOT互连结构。 垂直偏移通过引线框架实现，引线框架具有围绕模板的多个引线。 在引线指上形成第一导电层。 在引线指上形成第二导电层。 每个第二导电层定位成与第一导电层相邻，并且每个第一导电层定位成与第二导电层相邻。 第二导电层的高度大于第一导电层的高度。 第一和第二导电层可以具有并排布置或交错布置。 在第一和第二导电层上形成凸起。 接合线电连接到凸块。 半导体管芯安装在引线框架的管芯上并电连接到接合线和BOT互连结构。

公开(公告)号：US20120299165A1

公开(公告)日：2012-11-29

申请号：US13571020

申请日：2012-08-09

申请人： Reza A. Pagaila

发明人： Reza A. Pagaila

IPC分类号： H01L23/552

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

摘要： A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.

摘要翻译： 半导体器件具有部分地通过衬底形成的多个导电通孔。 导电层形成在衬底上并电连接到导电通孔。 半导体管芯安装在衬底上。 密封剂沉积在半导体管芯和衬底上。 通过半导体管芯周围的密封剂形成沟槽。 在密封剂上形成屏蔽层。 沟槽部分地形成穿过衬底，并且屏蔽层部分地通过衬底形成在沟槽中。 在形成屏蔽层之前，可以在沟槽中形成绝缘层。 去除衬底的一部分以暴露导电通孔。 在与半导体管芯相对的衬底上形成互连结构。 互连结构电连接到导电通孔。 屏蔽层电连接到互连结构。

公开(公告)号：US20120280403A1

公开(公告)日：2012-11-08

申请号：US13553739

申请日：2012-07-19

申请人： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang

发明人： Reza A. Pagaila ,  Byung Tai Do ,  Shuangwu Huang

IPC分类号： H01L23/48 ,  H01L25/07

CPC分类号： H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV.

公开(公告)号：US20120228749A1

公开(公告)日：2012-09-13

申请号：US13043179

申请日：2011-03-08

申请人： Reza A. Pagaila

发明人： Reza A. Pagaila

IPC分类号： H01L23/552 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L21/486 ,  H01L21/56 ,  H01L21/768 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

摘要： A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure.

摘要翻译： 半导体器件具有部分地通过衬底形成的多个导电通孔。 导电层形成在衬底上并电连接到导电通孔。 半导体管芯安装在衬底上。 密封剂沉积在半导体管芯和衬底上。 通过半导体管芯周围的密封剂形成沟槽。 在密封剂上形成屏蔽层。 沟槽部分地形成穿过衬底，并且屏蔽层部分地通过衬底形成在沟槽中。 在形成屏蔽层之前，可以在沟槽中形成绝缘层。 去除衬底的一部分以暴露导电通孔。 在与半导体管芯相对的衬底上形成互连结构。 互连结构电连接到导电通孔。 屏蔽层电连接到互连结构。

公开(公告)号：US08258012B2

公开(公告)日：2012-09-04

申请号：US12780295

申请日：2010-05-14

申请人： Reza A. Pagaila ,  Jose A. Caparas ,  Pandi C. Marimuthu

发明人： Reza A. Pagaila ,  Jose A. Caparas ,  Pandi C. Marimuthu

IPC分类号： H01L23/552

CPC分类号： H01L23/60 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/03

摘要： A semiconductor wafer has a plurality of semiconductor die separated by a saw street. The wafer is mounted to dicing tape. The wafer is singulated through the saw street to expose side surfaces of the semiconductor die. An ESD protection layer is formed over the semiconductor die and around the exposed side surfaces of the semiconductor die. The ESD protection layer can be a metal layer, encapsulant film, conductive polymer, conductive ink, or insulating layer covered by a metal layer. The ESD protection layer is singulated between the semiconductor die. The semiconductor die covered by the ESD protection layer are mounted to a temporary carrier. An encapsulant is deposited over the ESD protection layer covering the semiconductor die. The carrier is removed. An interconnect structure is formed over the semiconductor die and encapsulant. The ESD protection layer is electrically connected to the interconnect structure to provide an ESD path.

摘要翻译： 半导体晶片具有由锯条隔开的多个半导体管芯。 晶片安装在切割胶带上。 通过锯条将晶片分割，以露出半导体管芯的侧表面。 在半导体管芯上并围绕半导体管芯的暴露的侧表面形成ESD保护层。 ESD保护层可以是由金属层覆盖的金属层，密封剂膜，导电聚合物，导电油墨或绝缘层。 ESD保护层在半导体管芯之间分离。 由ESD保护层覆盖的半导体管芯被安装到临时载体上。 密封剂沉积在覆盖半导体管芯的ESD保护层上。 载体被移除。 在半导体管芯和密封剂上形成互连结构。 ESD保护层电连接到互连结构以提供ESD路径。