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    Capacitors using porous alumina structures
    131.
    发明授权
    Capacitors using porous alumina structures 有权
    使用多孔氧化铝结构的电容器

    公开(公告)号：US09076594B2

    公开(公告)日：2015-07-07

    申请号：US13797540

    申请日：2013-03-12

    Applicant: Invensas Corporation

    Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01G4/06 ,  H01G4/08 ,  H01G4/01 ,  H01G4/10 ,  H01L49/02 ,  H01M4/80

    CPC classification number: H01G4/33 ,  H01G4/01 ,  H01G4/08 ,  H01G4/10 ,  H01G4/385 ,  H01L28/60 ,  H01L28/92 ,  H01M4/80

    Abstract: Capacitors and methods of making the same are disclosed herein. In one embodiment, a capacitor comprises a structure having first and second oppositely facing surfaces and a plurality of pores each extending in a first direction from the first surface towards the second surface, and each having pore having insulating material extending along a wall of the pore; a first conductive portion comprising an electrically conductive material extending within at least some of the pores; and a second conductive portion comprising a region of the structure consisting essentially of aluminum surrounding individual pores of the plurality of pores, the second conductive portion electrically isolated from the first conductive portion by the insulating material extending along the walls of the pores.

    Abstract translation: 电容器及其制造方法在此公开。 在一个实施例中，电容器包括具有第一和第二相对面的表面和多个孔，每个孔从第一表面朝向第二表面沿第一方向延伸，并且每个孔具有沿孔的壁延伸的绝缘材料 ; 第一导电部分，包括在至少一些孔内延伸的导电材料; 以及第二导电部分，其包括主要由围绕所述多个孔的单个孔的铝构成的结构的区域，所述第二导电部分通过沿着所述孔的壁延伸的绝缘材料与所述第一导电部分电隔离。

    ULTRA HIGH PERFORMANCE INTERPOSER
    135.
    发明申请
    ULTRA HIGH PERFORMANCE INTERPOSER 有权
    超高性能插座

    公开(公告)号：US20150041988A1

    公开(公告)日：2015-02-12

    申请号：US13962349

    申请日：2013-08-08

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Zhuowen Sun

    IPC: H01L23/522 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.

    Abstract translation: 互连部件包括半导体材料层，其具有第一表面和与第一表面相对的第二表面，并且在第一方向上间隔开。 至少两个金属化通孔延伸穿过半导体材料层。 所述至少两个金属化通孔中的第一对在与第一方向正交的第二方向上彼此间隔开。 半导体层中的第一绝缘通孔从第一表面延伸到第二表面。 绝缘通孔被定位成使得绝缘通孔的几何中心在与第二方向正交的两个平面之间并且穿过第一对至少两个金属化通孔中的每一个。 电介质材料至少部分地填充第一绝缘通孔或至少部分地封闭绝缘通孔中的空隙。

    Direct-bonded LED structure contacts and substrate contacts
    137.
    发明授权
    Direct-bonded LED structure contacts and substrate contacts 有权

    公开(公告)号：US11329034B2

    公开(公告)日：2022-05-10

    申请号：US16840245

    申请日：2020-04-03

    Applicant: Invensas Corporation

    Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L21/18 ,  H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62

    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

    Advanced Device Assembly Structures And Methods
    138.
    发明申请
    Advanced Device Assembly Structures And Methods 有权

    公开(公告)号：US20220097166A1

    公开(公告)日：2022-03-31

    申请号：US17545322

    申请日：2021-12-08

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: B23K20/02 ,  H05K13/04 ,  H01L23/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/50 ,  B23K20/00 ,  H05K3/00 ,  H05K3/34

    Abstract: A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

    Structures And Methods For Low Temperature Bonding Using Nanoparticles
    140.
    发明申请
    Structures And Methods For Low Temperature Bonding Using Nanoparticles 有权

    公开(公告)号：US20210225801A1

    公开(公告)日：2021-07-22

    申请号：US17140519

    申请日：2021-01-04

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

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