公开(公告)号：US5545927A

公开(公告)日：1996-08-13

申请号：US440414

申请日：1995-05-12

Applicant: Mukta S. Farooq ,  Suryanarayana Kaja ,  Eric D. Perfecto ,  George E. White

Inventor： Mukta S. Farooq ,  Suryanarayana Kaja ,  Eric D. Perfecto ,  George E. White

IPC: H01L23/498 ,  H01L23/532 ,  H05K1/03 ,  H05K3/06 ,  H05K3/10 ,  H05K3/38 ,  H05K3/46 ,  H01L23/48

CPC classification number: H05K3/108 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2203/0597 ,  H05K2203/1105 ,  H05K3/062 ,  H05K3/388 ,  H05K3/4644

Abstract: The present invention relates generally to a new structure and method for capped copper electrical interconnects. More particularly, the invention encompasses a novel structure in which one or more of the copper electrical interconnects within a semiconductor substrate are capped to obtain a robust electrical interconnect structure. A method for obtaining such capped copper electrical interconnect structure is also disclosed. These capped interconnects can be a single layer or multi-layer structures. Similarly, the interconnect structure that is being capped can itself be composed of single or multi-layered material.

公开(公告)号：US5436412A

公开(公告)日：1995-07-25

申请号：US102027

申请日：1993-08-03

Applicant: Umar M. U. Ahmad ,  Ananda H. Kumar ,  Eric D. Perfecto ,  Chandrika Prasad ,  Sampath Purushothaman ,  Sudipta K. Ray

Inventor： Umar M. U. Ahmad ,  Ananda H. Kumar ,  Eric D. Perfecto ,  Chandrika Prasad ,  Sampath Purushothaman ,  Sudipta K. Ray

IPC: H01L23/12 ,  H01L23/32 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/113 ,  H01L23/49816 ,  H01L23/49866 ,  H01L23/5383 ,  H01L2224/48463 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H05K1/0306 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K3/0041 ,  H05K3/4076 ,  H05K3/4605 ,  H05K3/467

Abstract: An electrical interconnect structure for connecting a substrate to the next level of packaging or to a semiconductor device. The interconnect structure includes at least two layers of polymeric material, one of the layers having a capture pad and the second of the layers having a bonding pad electrically connected to the capture pad. The bonding pad and the second layer of polymeric material are at the same height so that the bonding pad is level with the second layer of polymeric material. Finally, there is a cap of electrically conducting metallization on the bonding pad and extending beyond the second layer of polymeric material. The cap is of a different composition than the bonding pad.

Abstract translation: 一种用于将衬底连接到下一级封装或半导体器件的电互连结构。 所述互连结构包括至少两层聚合材料，所述层中的一个具有捕获垫，并且所述层中的第二层具有电连接到所述捕获垫的接合焊盘。 接合焊盘和第二层聚合物材料处于相同的高度，使得焊盘与第二层聚合物材料平齐。 最后，在焊盘上存在导电金属化的帽，并延伸超过第二层聚合物材料。 盖子具有与接合垫不同的成分。

公开(公告)号：US5300403A

公开(公告)日：1994-04-05

申请号：US900975

申请日：1992-06-18

Applicant: Marie Angelopolus ,  Daniel G. Berger ,  Eric D. Perfecto ,  Peter J. Wilkens

Inventor： Marie Angelopolus ,  Daniel G. Berger ,  Eric D. Perfecto ,  Peter J. Wilkens

IPC: G03F7/038 ,  G03F7/40 ,  H01L21/027 ,  G03C5/00

CPC classification number: G03F7/40

Abstract: Standard processing techniques for creating a patterned polyimide film from a radiation sensitive polyimide film forming composition are modified to include a post-develop, flood exposure/hardening step which crosslinks precursors of the polyimide film prior to curing. The flood exposure/hardening step prevents pull-back of the wall profile which occurs during the shrinkage of radiation sensitive polyimide film forming composition which occurs during thermal curing.

Abstract translation: 用于从辐射敏感的聚酰亚胺膜形成组合物形成图案化聚酰亚胺膜的标准加工技术被修改为包括在固化之前交联聚酰亚胺膜的前体的后显影，泛光曝光/硬化步骤。 淹水/硬化步骤防止在热固化期间发生的辐射敏感性聚酰亚胺膜形成组合物的收缩期间发生的壁轮廓的拉回。

公开(公告)号：US08820612B2

公开(公告)日：2014-09-02

申请号：US13525855

申请日：2012-06-18

Applicant: Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

Inventor： Claudius Feger ,  Mark H. McLeod ,  Jae-Woong Nah ,  Eric D. Perfecto

IPC: B23K3/00 ,  B23K3/06

CPC classification number: B23K1/0016 ,  B23K1/20 ,  B23K3/0623 ,  B23K2101/42 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/68372 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11002 ,  H01L2224/11312 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/1403 ,  H01L2224/14505 ,  H01L2224/16237 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: Solder bumps of uniform height are provided on a substrate through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned layer of photoresist. Solder is injected over the pillars or BLM, filling the channels. The solder, which does not contain flux, is allowed to solidify. It forms a plurality of solder structures (bumps) of equal heights. Solder injection and solidification are preferably carried out in a nitrogen environment or a forming gas environment. Molten solder can be injected in channels formed in round wafers without spillage using a carrier assembly that accommodates such wafers and a fill head.

Abstract translation: 通过使用注射成型的焊料在基板上设置均匀高度的焊料凸块。 在图案化的光致抗蚀剂层的通道内的I / O焊盘上形成铜柱或极限极限冶金。 焊料注入柱子或BLM，填充通道。 允许不含焊剂的焊料固化。 它形成相同高度的多个焊料结构（凸块）。 焊接注入和固化优选在氮气环境或形成气体环境中进行。 可以使用容纳这种晶片和填充头的载体组件将熔融焊料注入到以圆形晶片形成的通道中而不会溢出。

公开(公告)号：US08742578B2

公开(公告)日：2014-06-03

申请号：US13552792

申请日：2012-07-19

Applicant: Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Jennifer D. Schuler

Inventor： Charles L. Arvin ,  Eric D. Perfecto ,  Wolfgang Sauter ,  Jennifer D. Schuler

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13139 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2224/81439 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/05552

Abstract: An integrated circuit (IC) chip including solder structures for connection to a package substrate, an IC chip package, and a method of forming the same are disclosed. In an embodiment, an IC chip is provided comprising a wafer having a plurality of solder structures disposed above the wafer. A ball limiting metallurgy (BLM) layer is disposed between each of the plurality of solder structures and the wafer. At least one of the plurality of solder structures has a first diameter and a first height, and at least one other solder structure has a second diameter and a second height. The differing heights and volumes of solder structures facilitate solder volume compensation for chip join improvement on the IC chip side rather than the package side.

Abstract translation: 公开了一种集成电路（IC）芯片，其包括用于连接到封装衬底的焊料结构，IC芯片封装及其形成方法。 在一个实施例中，提供一种IC芯片，其包括具有设置在晶片上方的多个焊料结构的晶片。 球限制冶金（BLM）层设置在多个焊料结构和晶片之间。 多个焊料结构中的至少一个具有第一直径和第一高度，并且至少一个其它焊料结构具有第二直径和第二高度。 焊料结构的不同高度和体积有助于在IC芯片侧而不是封装侧进行芯片连接改进的焊料体积补偿。

公开(公告)号：US20130252418A1

公开(公告)日：2013-09-26

申请号：US13874509

申请日：2013-05-01

Applicant: CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE J. MCCARTHY ,  ERIC D. PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA W. SEMKOW ,  THOMAS A. WASSICK

Inventor： CHARLES L. ARVIN ,  KENNETH BIRD ,  CHARLES C. GOLDSMITH ,  SUNG K. KANG ,  MINHUA LU ,  CLARE J. MCCARTHY ,  ERIC D. PERFECTO ,  SRINIVASA S.N. REDDY ,  KRYSTYNA W. SEMKOW ,  THOMAS A. WASSICK

IPC: H01L21/768

CPC classification number: H01L21/7685 ,  H01L21/321 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/0382 ,  H01L2224/0401 ,  H01L2224/11003 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/1131 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13562 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Abstract translation: 本发明的实施例包括无铅焊料互连结构和用于制造无铅互连结构的方法。 该结构包括具有最后金属层的半导体衬底，附着于最后金属层的铜基座，附着于铜基座的阻挡层，与阻挡层连接的阻挡保护层，以及与该阻挡层相接触的无铅焊料层 铜底座的最小一侧。

公开(公告)号：US06678949B2

公开(公告)日：2004-01-20

申请号：US09886326

申请日：2001-06-21

Applicant: Chandrika Prasad ,  Roy Yu ,  Richard L. Canull ,  Giulio DiGiacomo ,  Ajay P. Giri ,  Lewis S. Goldmann ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Voya R. Markovich ,  Eric D. Perfecto ,  Sampath Purushothaman ,  Joseph M. Sullivan

Inventor： Chandrika Prasad ,  Roy Yu ,  Richard L. Canull ,  Giulio DiGiacomo ,  Ajay P. Giri ,  Lewis S. Goldmann ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Voya R. Markovich ,  Eric D. Perfecto ,  Sampath Purushothaman ,  Joseph M. Sullivan

IPC: H05K334

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/16 ,  H01L23/49833 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K1/141 ,  H05K3/20 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/467 ,  H05K7/023 ,  H05K2201/049 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/0182 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49174 ,  Y10T29/49211 ,  Y10T29/49213 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A structure for mounting electronic devices. The structure uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract translation: 一种用于安装电子设备的结构。 该结构使用介于下面的载体和上覆薄膜之间的非导电的兼容间隔物。 间隔件包括通孔的图形，其与载体和薄膜的相对表面上的相对互连匹配。 以这种方式，焊接连接可以在通孔中延伸，以将薄膜电连接到载体上并平滑地形。 在用于形成结构的相关方法中，薄膜建立在第一牺牲载体上，然后在第二牺牲载体上进一步处理，以防止其在其加工期间变形，膨胀或以其它方式受到不利影响。 使用封闭的焊料接合工艺形成薄膜和载体之间的焊接连接。 间隔件与层压卡一起使用以在携带薄膜的卡的部分上产生热应力释放结构。

公开(公告)号：US06281452B1

公开(公告)日：2001-08-28

申请号：US09204851

申请日：1998-12-03

Applicant: Chandrika Prasad ,  Roy Yu ,  Richard L. Canull ,  Giulio DiGiacomo ,  Ajay P. Giri ,  Lewis S. Goldmann ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Voya R. Markovich ,  Eric D. Perfecto ,  Sampath Purushothaman ,  Joseph M. Sullivan

Inventor： Chandrika Prasad ,  Roy Yu ,  Richard L. Canull ,  Giulio DiGiacomo ,  Ajay P. Giri ,  Lewis S. Goldmann ,  Kimberley A. Kelly ,  Bouwe W. Leenstra ,  Voya R. Markovich ,  Eric D. Perfecto ,  Sampath Purushothaman ,  Joseph M. Sullivan

IPC: H01R1204

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/16 ,  H01L23/49833 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H05K1/141 ,  H05K3/20 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/467 ,  H05K7/023 ,  H05K2201/049 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/0182 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49174 ,  Y10T29/49211 ,  Y10T29/49213 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A structure for mounting electronic devices which uses a non-conductive, compliant spacer interposed between an underlying carrier and an overlying thin film. The spacer includes a pattern of through-vias which matches opposing interconnects on opposing surfaces of the carrier and the thin film. In this way, solder connections can extend in the through-vias to electrically connect the thin film to the carrier and smooth out topography. In a related process for forming the structure, the thin film is built on a first sacrificial carrier and then further processed on a second sacrificial carrier to keep it from distorting, expanding, or otherwise suffering adversely during its processing. The solder connections between the thin film and the carrier are formed using a closed solder joining process. The spacer is used with laminate cards to create thermal stress release structures on portions of the cards carrying a thin film.

Abstract translation: 一种用于安装电子器件的结构，其使用插入在下面的载体和上覆薄膜之间的非导电兼容间隔物。 间隔件包括通孔的图形，其与载体和薄膜的相对表面上的相对互连匹配。 以这种方式，焊接连接可以在通孔中延伸，以将薄膜电连接到载体上并平滑地形。 在用于形成结构的相关方法中，薄膜建立在第一牺牲载体上，然后在第二牺牲载体上进一步处理，以防止其在其加工期间变形，膨胀或以其它方式受到不利影响。 使用封闭的焊料接合工艺形成薄膜和载体之间的焊接连接。 间隔件与层压卡一起使用以在携带薄膜的卡的部分上产生热应力释放结构。

公开(公告)号：US5483105A

公开(公告)日：1996-01-09

申请号：US233025

申请日：1994-04-25

Applicant: Suryanarayana Kaja ,  Eric D. Perfecto ,  William H. Price ,  Sampath Purushothaman ,  Srinivasa N. Reddy ,  Vivek M. Sura ,  George E. White

Inventor： Suryanarayana Kaja ,  Eric D. Perfecto ,  William H. Price ,  Sampath Purushothaman ,  Srinivasa N. Reddy ,  Vivek M. Sura ,  George E. White

IPC: H01R12/32 ,  H01L23/498 ,  H01R12/04 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49811 ,  H05K1/111 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/09736 ,  H05K2201/098 ,  Y02P70/611

Abstract: A ceramic substrate pad used for establishing brazed connection between a pin and the substrate in the packaging of microelectronic semiconductor circuit chip. The pad is characterized by a stepped setback in the upper surface thereof which setback is oxidized to prevent wetting by the brazing alloy which bonds the pin to the pad. Stresses attributable to the brazing are isolated from the setback area and thus have reduced effect in causing cracking at the edges of the pad-substrate interface.

Abstract translation: 一种用于在微电子半导体电路芯片的封装中在引脚和衬底之间建立钎焊连接的陶瓷衬底焊盘。 该焊盘的特征在于在其上表面具有阶梯状的挫折，其挫折被氧化以防止通过将销钉固定到焊盘的钎焊合金的润湿。 由于钎焊产生的应力与塌陷区域隔离，因此在焊盘 - 衬底界面的边缘处产生破裂的效果降低。

公开(公告)号：US5464682A

公开(公告)日：1995-11-07

申请号：US166424

申请日：1993-12-14

Applicant: Eric D. Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George E. White

Inventor： Eric D. Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George E. White

IPC: H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  B32B9/00

CPC classification number: H05K1/116 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/0367 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/467 ,  Y10S428/901 ,  Y10T428/24926

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract translation: 一种器件包括陶瓷衬底。 在陶瓷衬底内的陶瓷通孔限定在不同于用于陶瓷通孔的设计的所需位置的实际位置。 最小捕获垫将实际位置与设计的所需位置电连通。 最小捕获垫包含陶瓷通孔接触部分，薄膜螺柱接触部分和连接部分; 并且三个中的每一个被配置为尽可能小以限制由捕获垫产生的电容。