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    UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY
    12.
    发明申请
    UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY 审中-公开

    公开(公告)号：US20180189188A1

    公开(公告)日：2018-07-05

    申请号：US15396460

    申请日：2016-12-31

    Applicant: Intel Corporation

    Inventor： MOHAN J. KUMAR ,  MURUGASAMY K. NACHIMUTHU

    IPC: G06F12/1009 ,  G06F3/06

    CPC classification number: G06F12/1009 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/067 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/261 ,  G06F2212/263 ,  G06F2212/657

    Abstract: Unified hardware and software two-level memory mechanisms and associated methods, systems, and software. Data is stored on near and far memory devices, wherein an access latency for a near memory device is less than an access latency for a far memory device. The near memory devices store data in data units having addresses in a near memory virtual address space, while the far memory devices store data in data units having addresses in a far memory address space, with a portion of the data being stored on both near and far memory devices. In response to memory read access requests, a determination is made to where data corresponding to the request is located on a near memory device, and if so the data is read from the near memory device; otherwise, the data is read from a far memory device. Memory access patterns are observed, and portions of far memory that are frequently accessed are copied to near memory to reduce access latency for subsequent accesses.

    Accelerator Resource Allocation and Pooling
    16.
    发明申请
    Accelerator Resource Allocation and Pooling 审中-公开

    公开(公告)号：US20180024757A1

    公开(公告)日：2018-01-25

    申请号：US15396151

    申请日：2016-12-30

    Applicant: INTEL CORPORATION

    Inventor： MOHAN J. KUMAR ,  MURUGASAMY K. NACHIMUTHU ,  AARON GORIUS ,  MICHAEL CROCKER

    IPC: G06F3/06

    Abstract: Examples may include techniques to allocate physical accelerator resources from pools of accelerator resources. In particular, virtual computing devices can be composed from physical resources and physical accelerator resources dynamically allocated to the virtual computing devices. The present disclosure provides that physical accelerator resources can be dynamically allocated, or composed, to a virtual computing device despite not being physically coupled to other components in the virtual device.

    ACCELERATING BOOT TIME ZEROING OF MEMORY BASED ON NON-VOLATILE MEMORY (NVM) TECHNOLOGY
    17.
    发明申请
    ACCELERATING BOOT TIME ZEROING OF MEMORY BASED ON NON-VOLATILE MEMORY (NVM) TECHNOLOGY 有权
    基于非易失性存储器（NVM）技术的加速引导存储器的时间归零

    公开(公告)号：US20150378615A1

    公开(公告)日：2015-12-31

    申请号：US14318573

    申请日：2014-06-27

    Applicant: Intel Corporation

    Inventor： RAJ K. RAMANUJAN ,  RAJESH M. SANKARAN ,  MURUGASAMY K. NACHIMUTHU ,  RICHARD P. MANGOLD

    IPC: G06F3/06 ,  G11C11/406

    CPC classification number: G06F3/0611 ,  G06F3/0625 ,  G06F3/0632 ,  G06F3/0679 ,  G06F8/71 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4416 ,  G06F11/1417 ,  G06F11/3476 ,  G11C7/20

    Abstract: Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device stores a boot version number corresponding to a portion of a non-volatile memory. A memory controller logic causes an update of the stored boot version number in response to each subsequent boot event. The memory controller logic returns a zero in response to a read operation directed at the portion of the non-volatile memory and a mismatch between the stored boot version number and a current boot version number. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了基于非易失性存储器（NVM）技术来加速引导时间归零的存储器的方法和装置。 在一个实施例中，存储设备存储对应于非易失性存储器的一部分的引导版本号。 存储器控制器逻辑导致响应于每个后续引导事件的存储的引导版本号的更新。 存储器控制器逻辑响应于针对非易失性存储器的部分的读操作和存储的引导版本号与当前引导版本号之间的不匹配而返回零。 还公开并要求保护其他实施例。

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