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公开(公告)号:US20120091574A1
公开(公告)日:2012-04-19
申请号:US12904506
申请日:2010-10-14
申请人: Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Meng-Wei CHOU , Hung-Jui KUO , Chung-Shi LIU
发明人: Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Meng-Wei CHOU , Hung-Jui KUO , Chung-Shi LIU
IPC分类号: H01L23/48 , H01L21/768
CPC分类号: H01L24/13 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0341 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03464 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05559 , H01L2224/05564 , H01L2224/05647 , H01L2224/1132 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11472 , H01L2224/13006 , H01L2224/13007 , H01L2224/13017 , H01L2224/13023 , H01L2224/13147 , H01L2224/16 , H01L2224/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/04941 , H01L2924/04953 , H01L2924/01028 , H01L2924/01044 , H01L2924/01025 , H01L2924/01022 , H01L2924/01032 , H01L2924/00 , H01L2224/05552
摘要: The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls.
摘要翻译: 本发明涉及半导体器件的凸块结构。 半导体器件的示例性结构包括衬底; 衬底上的接触垫; 钝化层,其在所述衬底上延伸,在所述接触焊盘上具有开口; 以及在所述钝化层的开口上的导电柱,其中所述导电柱包括基本上垂直于所述衬底的表面的上部和具有锥形侧壁的下部。
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公开(公告)号:US20120043654A1
公开(公告)日:2012-02-23
申请号:US12859379
申请日:2010-08-19
申请人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Chung-Shi LIU
发明人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Chung-Shi LIU
IPC分类号: H01L23/498 , H01L21/768
CPC分类号: H01L21/2885 , C25D5/022 , C25D5/10 , C25D17/12 , H01L21/76877 , H01L21/76885 , H01L23/525 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L24/14 , H01L2224/0345 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05572 , H01L2224/05647 , H01L2224/06102 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11823 , H01L2224/11825 , H01L2224/11912 , H01L2224/13005 , H01L2224/13022 , H01L2224/13083 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13562 , H01L2224/13582 , H01L2224/13611 , H01L2224/13655 , H01L2224/1403 , H01L2224/141 , H01L2224/742 , H01L2224/81193 , H01L2224/81194 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/01046 , H01L2924/04953 , H01L2924/04941 , H01L2924/01028 , H01L2924/0105 , H01L2924/00 , H01L2224/05552
摘要: The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration.
摘要翻译: 通过使用图案化阳极描述的制备凸块结构的机理可以简化凸块制造工艺,降低制造成本,并且改善晶片内和晶片之间的厚度均匀性。 此外,上述机构允许形成具有不同高度的凸块,以允许凸块与不同高度的基板上的元件一体化。 具有不同高度的冲击扩大了铜柱凸起的应用,以实现进一步的芯片集成。
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13.
公开(公告)号:US20110254151A1
公开(公告)日:2011-10-20
申请号:US12761863
申请日:2010-04-16
申请人: Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Chung-Shi LIU
发明人: Chih-Wei LIN , Ming-Da CHENG , Wen-Hsiung LU , Chung-Shi LIU
IPC分类号: H01L23/498 , H01L21/3205
CPC分类号: C23C18/1605 , C23C18/165 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05572 , H01L2224/05647 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11849 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13155 , H01L2224/13164 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/81193 , H01L2224/81447 , H01L2924/0002 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/01046 , H01L2924/00 , H01L2224/05552
摘要: A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile.
摘要翻译: 用于制造没有UBM底切的凸块结构的方法使用无电镀铜工艺在光致抗蚀剂层的开口内的Ti UBM层上选择性地形成Cu UBM层。 在剥离光致抗蚀剂层之后,不需要对Cu UBM层进行湿蚀刻处理,从而UBM结构具有非底切轮廓。
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14.
公开(公告)号:US20120007228A1
公开(公告)日:2012-01-12
申请号:US12832231
申请日:2010-07-08
申请人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Ming-Che HO , Chung-Shi LIU
发明人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Ming-Che HO , Chung-Shi LIU
IPC分类号: H01L23/498 , H01L21/768 , H01L23/00
CPC分类号: H01L24/13 , H01L21/563 , H01L23/3192 , H01L24/05 , H01L24/11 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05166 , H01L2224/05572 , H01L2224/05573 , H01L2224/05647 , H01L2224/1132 , H01L2224/11424 , H01L2224/1145 , H01L2224/11462 , H01L2224/1147 , H01L2224/13076 , H01L2224/1308 , H01L2224/13083 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13582 , H01L2224/136 , H01L2224/13647 , H01L2224/16145 , H01L2224/16225 , H01L2224/73204 , H01L2224/97 , H01L2225/06513 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10272 , H01L2924/10329 , H01L2924/10335 , H01L2924/14 , H01L2924/3512 , H01L2224/13655 , H01L2224/81 , H01L2224/13099 , H01L2924/00 , H01L2224/05552
摘要: An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer.
摘要翻译: 本公开的实施例包括半导体管芯上的导电柱。 提供基板。 焊盘在衬底上。 导电支柱位于接合垫上方。 导电柱具有顶表面,边缘侧壁和高度。 覆盖层在导电柱的顶表面之上。 盖层沿着导电柱的边缘侧壁延伸一段长度。 焊料材料在覆盖层的顶表面之上。
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公开(公告)号:US20110101527A1
公开(公告)日:2011-05-05
申请号:US12846353
申请日:2010-07-29
申请人: Ming-Da CHENG , Wen-Hsiung LU , Chih-Wei LIN , Ching-Wen CHEN , Yi-Wen WU , Chia-Tung CHANG , Ming-Che HO , Chung-Shi LIU
发明人: Ming-Da CHENG , Wen-Hsiung LU , Chih-Wei LIN , Ching-Wen CHEN , Yi-Wen WU , Chia-Tung CHANG , Ming-Che HO , Chung-Shi LIU
IPC分类号: H01L23/498 , H01L21/60
CPC分类号: H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05572 , H01L2224/05647 , H01L2224/10145 , H01L2224/1145 , H01L2224/11452 , H01L2224/1146 , H01L2224/1147 , H01L2224/11827 , H01L2224/13006 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13147 , H01L2224/13647 , H01L2224/16225 , H01L2224/16227 , H01L2224/16507 , H01L2224/81191 , H01L2224/81815 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01051 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/3651 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/05 , H01L2924/00012 , H01L2924/01083 , H01L2924/00 , H01L2224/05552
摘要: The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper.
摘要翻译: 上述形成金属凸块结构的机构解决了基板上的导电层与连接到导电层的金属凸块之间的分层问题。 导电层可以是金属焊盘,后钝化互连(PPI)层或顶层金属层。 通过在导电层(或基底导电层)上进行保护性导电层的原位沉积,金属凸块的凸块下金属(UBM)层更好地粘附到导电层并减少界面分层的发生。 在一些实施例中,可以去除UBM层中的铜扩散阻挡子层。 在一些其它实施例中,如果通过非电镀工艺沉积金属凸块并且金属凸块不是由铜制成的,则不需要UBM层。
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公开(公告)号:US20110260317A1
公开(公告)日:2011-10-27
申请号:US12765250
申请日:2010-04-22
申请人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Jacky CHANG , Chung-Shi LIU , Chen-Hua YU
发明人: Wen-Hsiung LU , Ming-Da CHENG , Chih-Wei LIN , Jacky CHANG , Chung-Shi LIU , Chen-Hua YU
IPC分类号: H01L23/50 , H01L21/768
CPC分类号: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0346 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05572 , H01L2224/11452 , H01L2224/11462 , H01L2224/1147 , H01L2224/11823 , H01L2224/11825 , H01L2224/11906 , H01L2224/13022 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13099 , H01L2224/13147 , H01L2224/13455 , H01L2224/13565 , H01L2224/1357 , H01L2224/13639 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2924/0001 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要: A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer.
摘要翻译: 铜柱凸起具有由电解金属层形成的侧壁保护层。 电解金属层是电解镍层,电解金层,电解铜层或电解银层。
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公开(公告)号:US20130309621A1
公开(公告)日:2013-11-21
申请号:US13475790
申请日:2012-05-18
申请人: Hui-Min HUANG , Chih-Wei LIN , Wen-Hsiung LU , Ming-Da CHENG , Chung-Shi LIU
发明人: Hui-Min HUANG , Chih-Wei LIN , Wen-Hsiung LU , Ming-Da CHENG , Chung-Shi LIU
IPC分类号: H01L21/687 , F27D19/00 , F27D5/00
CPC分类号: H01L21/67288 , H01L21/6838
摘要: A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.
摘要翻译: 一种用于调整晶片翘曲的方法,包括提供具有中心部分和边缘部分的晶片,并提供其上具有用于保持晶片的保持区域的保持台。 将晶片放置在保持台上,其中心部分高于边缘部分,然后按压到保持区域上,使得晶片通过自吸力被吸引并保持在保持台上。 根据晶片的翘曲量将晶片在预定温度下加热预定时间,以便实现基本上平坦的晶片或预定的晶片级。
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公开(公告)号:US20130093076A1
公开(公告)日:2013-04-18
申请号:US13272434
申请日:2011-10-13
申请人: Wei-Hung LIN , Ming-Da CHENG , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU
发明人: Wei-Hung LIN , Ming-Da CHENG , Chung-Shi LIU , Mirng-Ji LII , Chen-Hua YU
IPC分类号: H01L23/498 , B23K1/20
CPC分类号: H01L23/49894 , H01L21/4864 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05647 , H01L2224/13082 , H01L2224/13111 , H01L2224/13147 , H01L2224/16238 , H01L2224/73204 , H01L2224/81022 , H01L2224/81191 , H01L2224/81815 , H01L2924/1305 , H01L2924/13091 , H01L2924/00014 , H01L2924/01073 , H01L2924/01049 , H01L2924/0105 , H01L2924/0103 , H01L2924/01025 , H01L2924/01024 , H01L2924/01022 , H01L2924/01032 , H01L2924/01038 , H01L2924/01078 , H01L2924/01012 , H01L2924/01013 , H01L2924/0104 , H01L2924/01047 , H01L2924/01029 , H01L2924/00012 , H01L2924/01082 , H01L2924/01083 , H01L2924/01079 , H01L2924/01051 , H01L2924/04941 , H01L2924/04953 , H01L2924/00
摘要: A method of a semiconductor package includes providing a substrate having a conductive trace coated with an organic solderability preservative (OSP) layer, removing the OSP layer from the conductive trace, and then coupling a chip to the substrate to form a semiconductor package.
摘要翻译: 半导体封装的方法包括提供具有涂覆有有机可焊性防腐剂(OSP)层的导电迹线的衬底,从导电迹线去除OSP层,然后将芯片耦合到衬底以形成半导体封装。
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公开(公告)号:US20110278716A1
公开(公告)日:2011-11-17
申请号:US12778610
申请日:2010-05-12
申请人: Chun-Lei HSU , Ming-Che HO , Ming-Da CHENG , Chung-Shi LIU
发明人: Chun-Lei HSU , Ming-Che HO , Ming-Da CHENG , Chung-Shi LIU
IPC分类号: H01L23/485 , H01L21/60
CPC分类号: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03424 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05559 , H01L2224/05571 , H01L2224/05572 , H01L2224/1145 , H01L2224/11452 , H01L2224/11462 , H01L2224/1148 , H01L2224/1161 , H01L2224/11616 , H01L2224/11831 , H01L2224/13005 , H01L2224/13022 , H01L2224/1308 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13169 , H01L2924/00013 , H01L2924/0002 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/00014 , H01L2924/01014 , H01L2924/206 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要: A method for fabricating bump structure forms an under-bump metallurgy (UBM) layer in an opening of an encapsulating layer, and then forms a bump layer on the UBM layer within the opening of the encapsulating layer. After removing excess material of the bump layer from the upper surface of the encapsulating layer, the encapsulating layer is removed till a top portion of the bump layer protrudes from the upper surface of the encapsulating layer.
摘要翻译: 一种用于制造凸块结构的方法在封装层的开口中形成凸起下金属(UBM)层,然后在封装层的开口内的UBM层上形成凸点层。 在从封装层的上表面除去突起层的多余材料之后,去除封装层直到凸起层的顶部从封装层的上表面突出。
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公开(公告)号:US20130187269A1
公开(公告)日:2013-07-25
申请号:US13427787
申请日:2012-03-22
申请人: Hung-Jen LIN , Tsung-Ding WANG , Chien-Hsiun LEE , Wen-Hsiung LU , Ming-Da CHENG , Chung-Shi LIU
发明人: Hung-Jen LIN , Tsung-Ding WANG , Chien-Hsiun LEE , Wen-Hsiung LU , Ming-Da CHENG , Chung-Shi LIU
IPC分类号: H01L23/498 , H01L21/56
CPC分类号: H01L24/81 , H01L21/563 , H01L21/565 , H01L21/566 , H01L21/768 , H01L23/3114 , H01L23/3171 , H01L23/525 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/83 , H01L24/92 , H01L24/94 , H01L2224/02311 , H01L2224/0239 , H01L2224/024 , H01L2224/0347 , H01L2224/03612 , H01L2224/03614 , H01L2224/0362 , H01L2224/0401 , H01L2224/05008 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05582 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/21 , H01L2224/27318 , H01L2224/27334 , H01L2224/27416 , H01L2224/2919 , H01L2224/73204 , H01L2224/81024 , H01L2224/81191 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2224/83192 , H01L2224/83855 , H01L2224/92125 , H01L2224/94 , H01L2924/00014 , H01L2924/01013 , H01L2924/01047 , H01L2924/12042 , H01L2924/181 , H01L2924/2076 , H01L2224/81 , H01L2924/01029 , H01L2924/04941 , H01L2924/04953 , H01L2924/014 , H01L2224/11 , H01L2924/00
摘要: A package assembly including a semiconductor die electrically coupled to a substrate by an interconnected joint structure. The semiconductor die includes a bump overlying a semiconductor substrate, and a molding compound layer overlying the semiconductor substrate and being in physical contact with a first portion of the bump. The substrate includes a no-flow underfill layer on a conductive region. A second portion of the bump is in physical contact with the no-flow underfill layer to form the interconnected joint structure.
摘要翻译: 一种包装组件,其包括通过互连的接合结构电耦合到衬底的半导体管芯。 半导体管芯包括覆盖半导体衬底的凸块和覆盖半导体衬底并与凸点的第一部分物理接触的模塑复合层。 衬底包括导电区域上的无流动底部填充层。 凸块的第二部分与无流动底部填充层物理接触以形成互连的连接结构。
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