公开(公告)号：US10062656B2

公开(公告)日：2018-08-28

申请号：US15236526

申请日：2016-08-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chao-Ching Chang ,  Sheng-Chan Li ,  Wen-Jen Tsai ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Yi-Ming Lin ,  Min-Hui Lin

IPC分类号： H01L23/00

CPC分类号： H01L24/02 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/02331 ,  H01L2224/0237 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/80001 ,  H01L2224/80895 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A semiconductor device includes a substrate, a dielectric structure, a top metal layer and a bonding structure. The dielectric structure is disposed on the substrate. The top metal layer is disposed in the dielectric structure. The bonding structure is disposed on the dielectric structure and the top metal layer. The bonding structure includes a silicon oxide layer, a silicon oxy-nitride layer, a conductive bonding layer and a barrier layer. The silicon oxide layer is disposed on the dielectric structure. The silicon oxy-nitride layer covers the silicon oxide layer. The conductive bonding layer is disposed in the silicon oxide layer and the silicon oxy-nitride layer. The barrier layer covers a sidewall and a bottom of the conductive bonding layer.

公开(公告)号：US09837346B2

公开(公告)日：2017-12-05

申请号：US15459648

申请日：2017-03-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kuo Lung Pan ,  Yu-Feng Chen ,  Chen-Shien Chen

IPC分类号： H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02251 ,  H01L2224/0226 ,  H01L2224/10175 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13687 ,  H01L2224/1411 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81805 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/05042 ,  H01L2924/0541 ,  H01L2924/014 ,  H01L2924/00014

摘要： An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures, each including an outer insulating layer over a conductive material, are disposed proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die, the microstructures preventing spread of the underfill. In another example method, a via can be formed in a substrate and the substrate etched to form a bump or pillar from the via. An insulating material can be formed over the bump or pillar. In another example method, a photoresist deposited over a seed layer and patterned to form openings. A conductive material is plated in the openings, forming a plurality of pillars or bumps. The photoresist and exposed seed layer are removed. The conductive material is oxidized to form an insulating material.

公开(公告)号：US20160293532A1

公开(公告)日：2016-10-06

申请号：US15180892

申请日：2016-06-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Wei Wu ,  Szu Wei Lu ,  Jing-Cheng Lin

IPC分类号： H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L21/768 ,  H01L21/78 ,  H01L23/14 ,  H01L21/56 ,  H01L23/00

CPC分类号： H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

摘要翻译： 半导体封装包括具有前侧，后侧和背面上的角部区域的插入器芯片，其由插入器芯片的第一角边缘和第二拐角边缘限定。 芯片结合到插入器芯片的前侧。 在插入器芯片的背面的拐角区域上形成至少一个坝结构。 坝结构包括与插入器芯片的第一角边缘和第二拐角边缘中的至少一个对准的边缘。

公开(公告)号：US20160086900A1

公开(公告)日：2016-03-24

申请号：US14961663

申请日：2015-12-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Kuo

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/78

CPC分类号： H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.

摘要翻译： 公开了半导体器件及其制造方法。 在一些实施例中，半导体器件包括衬底和设置在衬底上的多个接触焊盘。 接触垫可以布置在球栅阵列（BGA）中，并且可以包括多个拐角。 围绕多个拐角的每一个，例如BGA的拐角设置一个金属水坝。

公开(公告)号：US09252080B1

公开(公告)日：2016-02-02

申请号：US14514640

申请日：2014-10-15

申请人： GLOBALFOUNDRIES INC.

发明人： Daniel J. Couture ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Anthony K. Stamper

IPC分类号： H01L21/24 ,  H01L23/48 ,  H01L21/768 ,  H01L21/321

CPC分类号： H01L23/481 ,  H01L21/3212 ,  H01L21/76816 ,  H01L21/76834 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/02125 ,  H01L2224/0226 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/05442

摘要： An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.

摘要翻译： 在空隙区域上形成用于介电层的半导体结构的方法包括确定形貌半导体特征的空隙区域的位置。 第二电介质层沉积在第一介电层和地形半导体特征的顶表面上。 将第二介电层图案化成一个或多个部分，其中图案化的第二介电层的至少一部分在形貌半导体特征的空隙区域的位置之上。 第一金属层沉积在第二电介质层上，第一介电层的至少一部分和形貌半导体特征的顶表面的一部分。 执行第一金属层的化学机械抛光，其中化学机械抛光剂到达第二介电层的一个或多个部分中的至少一个的顶表面。

公开(公告)号：US09093393B2

公开(公告)日：2015-07-28

申请号：US14083834

申请日：2013-11-19

申请人： J-DEVICES CORPORATION

发明人： Toru Suda

IPC分类号： H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/14 ,  H01L23/556 ,  H01L23/498

CPC分类号： H01L23/3157 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3192 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/556 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/00 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02245 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/11462 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device includes a rectangular lower semiconductor element; a plurality of external electrodes located in a pattern on the lower semiconductor element along sides thereof; a plurality of internal electrodes electrically connected to the plurality of external electrodes via a plurality of line patterns respectively and located on the lower semiconductor element in a pattern; dams provided in such a pattern that each of the dams encloses one or at least two external electrodes among the plurality of external electrodes; an upper semiconductor element mounted on the lower semiconductor element such that a plurality of terminals on the upper semiconductor element are electrically connected to the plurality of internal electrodes respectively; and a resin potted to flow to a space between the lower semiconductor element and the upper semiconductor element.

摘要翻译： 半导体器件包括矩形下半导体元件; 多个外部电极，沿其侧面位于下部半导体元件上的图案中; 多个内部电极经由多个线图案电连接到所述多个外部电极，并以图案位于所述下部半导体元件上; 堤坝以这样的图案提供，使得每个坝围绕多个外部电极中的一个或至少两个外部电极; 上半导体元件，其安装在所述下半导体元件上，使得所述上半导体元件上的多个端子分别电连接到所述多个内部电极; 以及被封装以流到下半导体元件和上半导体元件之间的空间的树脂。

公开(公告)号：US20150132941A1

公开(公告)日：2015-05-14

申请号：US14604503

申请日：2015-01-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/00

CPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

摘要翻译： 公开了一种用于形成半导体管芯接触结构的系统和方法。 一个实施例包括顶层金属接触，例如铜，其厚度足够大以充当底层低k，极低k或超低k电介质层的缓冲器。 可以在顶层金属接触件上方形成接触焊盘或后钝化互连，并且可以形成铜柱或焊料凸块以与顶层金属接触件电连接。

公开(公告)号：US08928156B2

公开(公告)日：2015-01-06

申请号：US14306327

申请日：2014-06-17

申请人： Rohm Co., Ltd.

发明人： Osamu Miyata ,  Masaki Kasai ,  Shingo Higuchi

IPC分类号： H01L23/48 ,  H01L23/29

CPC分类号： H01L23/3178 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/528 ,  H01L23/544 ,  H01L23/562 ,  H01L24/02 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L2223/5446 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/10161 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/182 ,  H01L2924/186 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014 ,  H01L2924/00012

摘要： An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

摘要翻译： 本发明的半导体器件包括具有钝化膜的半导体芯片和设置在钝化膜上方的密封树脂层，用于密封半导体芯片的正面。 密封树脂层延伸到钝化膜的侧表面以覆盖侧表面。

公开(公告)号：US20120038046A1

公开(公告)日：2012-02-16

申请号：US12836612

申请日：2010-08-13

申请人： How Lin ,  Frank Egitto ,  Voya Markovich

发明人： How Lin ,  Frank Egitto ,  Voya Markovich

IPC分类号： H01L23/48 ,  H01L21/447

CPC分类号： H01L23/3157 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/72 ,  H01L2224/0226 ,  H01L2224/02335 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73251 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81901 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72

摘要： A method of forming a compressible contact structure on a semi-conductor chip which comprises bonding a compressible polymer layer to the chip's surface, forming a plurality of openings within the layer, depositing electrically conductive material within the openings to form electrical connections with the chip's contacts, forming a plurality of electrically conductive line elements on the polymer layer extending from a respective opening and each including an end portion, and forming a plurality of contact members each on a respective one of the line segment end portions. The compressible polymer layer allows the contact members to deflect toward (compress) the chip when the contact members are engaged by an external force or forces. A semi-conductor chip including such a compressible contact structure is also provided.

摘要翻译： 一种在半导体芯片上形成可压缩接触结构的方法，包括将可压缩的聚合物层粘合到芯片的表面，在该层内形成多个开口，在开口内沉积导电材料以形成与芯片的触点的电连接 在聚合物层上形成多个导电线元件，所述多个导电线元件从相应的开口延伸并且各自包括端部，并且在所述线段端部中的相应一个上形成多个接触元件。 当可接触构件通过外力或力接合时，可压缩聚合物层允许接触构件偏转（压缩）芯片。 还提供了包括这种可压缩接触结构的半导体芯片。

公开(公告)号：US20110101520A1

公开(公告)日：2011-05-05

申请号：US12846214

申请日：2010-07-29

申请人： Chung-Shi Liu ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L23/48 ,  H01L23/481 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0225 ,  H01L2224/0226 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13018 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/19041 ,  H01L2924/35121 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact.

摘要翻译： 公开了一种用于形成半导体管芯接触结构的系统和方法。 一个实施例包括顶层金属接触，例如铜，其厚度足够大以充当底层低k，极低k或超低k电介质层的缓冲器。 可以在顶层金属接触件上方形成接触焊盘或后钝化互连，并且可以形成铜柱或焊料凸块以与顶层金属接触件电连接。