公开(公告)号：US20160351486A1

公开(公告)日：2016-12-01

申请号：US14722872

申请日：2015-05-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JinHee Jung ,  HyungSang Park ,  SungSoo Kim

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L28/40 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/185 ,  H05K3/4664 ,  H05K2201/10015

Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

Abstract translation: 半导体器件包括第一导电层。 在第一导电层上形成第二导电层。 半导体部件设置在第一导电层上。 第二导电层位于半导体部件的顶表面和半导体部件的底表面之间的平面中。 在与第一导电层相对的半导体部件上形成第三导电层。 半导体器件包括对称结构。 在第一导电层和半导体部件之间形成第一绝缘层。 在半导体部件和第三导电层之间形成第二绝缘层。 第一导电层和半导体部件之间的第一绝缘层的高度在半导体部件和第三导电层之间的第二绝缘层的高度的90％至110％之间。 半导体部件包括无源器件。

公开(公告)号：US20160276307A1

公开(公告)日：2016-09-22

申请号：US14660840

申请日：2015-03-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L25/16 ,  H01L23/552 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/568 ,  H01L22/14 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Abstract translation: PoP半导体器件具有设置在底部半导体封装上的顶部半导体封装。 顶部半导体封装具有衬底和设置在衬底上的第一半导体管芯。 第一和第二密封剂沉积在第一半导体管芯和衬底上。 在沉积第二密封剂之后，在衬底上形成第一叠层互连结构。 顶部包装被放置在底部包装上。 底部封装具有设置在第二半导体管芯周围的第二半导体管芯和模块化互连单元。 在第二半导体管芯和模块化互连单元上形成第二堆叠互连结构。 模块化互连单元包括多个导电通孔和电连接到导电通孔的多个接触垫。 顶部半导体封装上的积聚互连结构的I / O图案被设计成与模块化互连单元的I / O模式一致。

公开(公告)号：US09449932B2

公开(公告)日：2016-09-20

申请号：US13886556

申请日：2013-05-03

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Arnel Trasporto ,  Linda Pei Ee Chua ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L24/14 ,  H01L21/4832 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10175 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/06558 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2224/05099 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a base substrate with recesses formed in a first surface of the base substrate. A first conductive layer is formed over the first surface and into the recesses. A second conductive layer is formed over a second surface of the base substrate. A first semiconductor die is mounted to the base substrate with bumps partially disposed within the recesses over the first conductive layer. A second semiconductor die is mounted to the first semiconductor die. Bond wires are formed between the second semiconductor die and the first conductive layer over the first surface of the base substrate. An encapsulant is deposited over the first and second semiconductor die and base substrate. A portion of the base substrate is removed from the second surface between the second conductive layer down to the recesses to form electrically isolated base leads for the bumps and bond wires.

公开(公告)号：US09443829B2

公开(公告)日：2016-09-13

申请号：US14728182

申请日：2015-06-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L23/552 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/11 ,  H01L24/16 ,  H01L24/19 ,  H01L24/24 ,  H01L24/25 ,  H01L24/81 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/81805

Abstract: A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.

公开(公告)号：US09443828B2

公开(公告)日：2016-09-13

申请号：US14694811

申请日：2015-04-23

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/538 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00

Abstract: A semiconductor device has a first thermally conductive layer formed over a first surface of a semiconductor die. A second surface of the semiconductor die is mounted to a sacrificial carrier. An encapsulant is deposited over the first thermally conductive layer and sacrificial carrier. The encapsulant is planarized to expose the first thermally conductive layer. A first insulating layer is formed over the second surface of the semiconductor die and a first surface of the encapsulant. A portion of the first insulating layer over the second surface of the semiconductor die is removed. A second thermally conductive layer is formed over the second surface of the semiconductor die within the removed portion of the first insulating layer. An electrically conductive layer is formed within the insulating layer around the second thermally conductive layer. A heat sink can be mounted over the first thermally conductive layer.

公开(公告)号：US09443762B2

公开(公告)日：2016-09-13

申请号：US13933406

申请日：2013-07-02

Applicant: STATS ChipPAC, Ltd.

Inventor： Pandi C. Marimuthu ,  Shuangwu Huang ,  Nathapong Suthiwongsunthorn

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L21/76898 ,  H01L21/302 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76885 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/02 ,  H01L24/04 ,  H01L24/05 ,  H01L24/06 ,  H01L24/10 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/10125 ,  H01L2224/1184 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/1301 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14104 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/1058 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/11849 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

公开(公告)号：US09406647B2

公开(公告)日：2016-08-02

申请号：US14214120

申请日：2014-03-14

Applicant: STATS ChipPAC, Ltd.

Inventor： Byung Tai Do ,  Heap Hoe Kuan

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/00 ,  H01L21/683 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/97 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3185 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/96 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13138 ,  H01L2224/13147 ,  H01L2224/14131 ,  H01L2224/20 ,  H01L2224/96 ,  H01L2924/01002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00014

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract translation: 半导体器件首先通过锯切街道引导件提供晶片，并且具有形成在晶片的有效表面上的接合焊盘。 晶片用切割胶带胶带。 将晶片沿着锯条导轨分割为具有在多个模具中的每一个之间具有多个间隙的多个模具。 切割带被拉伸以将多个间隙扩展到预定距离。 有机材料沉积在多个间隙中的每一个中。 有机材料的顶表面与多个管芯的第一管芯的顶表面基本共面。 重分布层在有机材料的一部分上被图案化。 凹凸金属化（UBM）通过再分配层与接合焊盘电连接在有机材料上沉积。

公开(公告)号：US20160214857A1

公开(公告)日：2016-07-28

申请号：US15008347

申请日：2016-01-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/096 ,  H01L2224/48091 ,  H01L2924/15151 ,  H01L2924/00014

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Abstract translation: 微机电系统（MEMS）半导体器件具有第一和第二半导体管芯。 第一半导体管芯与模块化互连单元一起嵌入密封剂内。 或者，第一半导体管芯被嵌入到衬底内。 第二半导体管芯，例如MEMS管芯，设置在第一半导体管芯上，并通过互连结构电连接到第一半导体管芯。 在另一个实施例中，第一半导体管芯是倒装芯片安装到衬底，并且第二半导体管芯与第一半导体管芯相邻的衬底引线接合。 在另一个实施例中，第一和第二半导体管芯被嵌入密封剂中并通过堆积互连结构电连接。 盖子设置在半导体管芯上。 在MEMS麦克风实施例中，盖，基板或互连结构包括在MEMS管芯的表面上的开口。

公开(公告)号：US09397236B2

公开(公告)日：2016-07-19

申请号：US14021208

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Zigmund R. Camacho ,  Henry D. Bathan ,  Lionel Chien Hui Tay ,  Arnel Senosa Trasporto

IPC: H01L31/02 ,  H01L31/0203 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L31/0203 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/32 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

公开(公告)号：US09385102B2

公开(公告)日：2016-07-05

申请号：US13630912

申请日：2012-09-28

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen ,  Yu Gu

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/03

Abstract: A semiconductor device includes a semiconductor die. An encapsulant is formed around the semiconductor die. A build-up interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A first supporting layer is formed over a second surface of the semiconductor die as a supporting substrate or silicon wafer disposed opposite the build-up interconnect structure. A second supporting layer is formed over the first supporting layer an includes a fiber enhanced polymer composite material comprising a footprint including an area greater than or equal to an area of a footprint of the semiconductor die. The semiconductor die comprises a thickness less than 450 micrometers (μm). The thickness of the semiconductor die is at least 1 μm less than a difference between a total thickness of the semiconductor device and a thickness of the build-up interconnect structure and the second supporting layer.

Abstract translation: 半导体器件包括半导体管芯。 在半导体管芯周围形成密封剂。 在半导体管芯和密封剂的第一表面上形成积聚互连结构。 第一支撑层形成在半导体管芯的第二表面上，作为与积聚互连结构相对设置的支撑衬底或硅晶片。 在第一支撑层上形成第二支撑层，包括纤维增强聚合物复合材料，其包括占地面积，该占地面积大于或等于半导体管芯的覆盖区域的面积。 半导体管芯的厚度小于450微米（μm）。 半导体管芯的厚度比半导体器件的总厚度和积层互连结构和第二支撑层的厚度之差小至少1μm。