Patent search ap:("INVENSAS CORPORATION") AND inv:"Cyprian Emeka UZOH" Page 3

21.

发明申请
INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION AGAINST MECHANICAL THINNING AND FOR OTHER PURPOSES, AND METHODS OF FABRICATING SUCH ASSEMBLIES 有权

公开(公告)号：US20170084539A1

公开(公告)日：2017-03-23

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian GAO , Cyprian Emeka UZOH , Charles G. WOYCHIK , Hong SHEN , Arkalgud R. SITARAM , Liang WANG , Akash AGRAWAL , Rajesh KATKAR

IPC: H01L23/538 , H01L23/31 , H01L21/48

CPC classification number: H01L23/5385 , H01L21/486 , H01L21/6835 , H01L23/147 , H01L23/15 , H01L23/3128 , H01L23/3135 , H01L23/49827 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/83 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2221/68331 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/08225 , H01L2224/16225 , H01L2224/16227 , H01L2224/32105 , H01L2224/32106 , H01L2224/32225 , H01L2224/48091 , H01L2224/48101 , H01L2224/48105 , H01L2224/48137 , H01L2224/48227 , H01L2224/49097 , H01L2224/73204 , H01L2924/00014 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/351 , H01L2924/3511 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

22.

发明申请
CONDUCTIVE CONNECTIONS, STRUCTURES WITH SUCH CONNECTIONS, AND METHODS OF MANUFACTURE 审中-公开

公开(公告)号：US20160336286A1

公开(公告)日：2016-11-17

申请号：US15221370

申请日：2016-07-27

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR , Cyprian Emeka UZOH

IPC: H01L23/00 , H05K3/34 , H05K1/14 , H01L25/10 , H01L25/00

CPC classification number: H01L24/14 , B23K1/0016 , B23K3/0623 , B23K35/0244 , B23K35/0266 , B23K2101/40 , H01L21/02225 , H01L21/4853 , H01L21/56 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3135 , H01L23/49811 , H01L23/49816 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/742 , H01L24/81 , H01L24/83 , H01L24/98 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/03318 , H01L2224/0332 , H01L2224/0333 , H01L2224/0391 , H01L2224/05022 , H01L2224/05073 , H01L2224/0508 , H01L2224/051 , H01L2224/05567 , H01L2224/056 , H01L2224/06102 , H01L2224/10145 , H01L2224/11001 , H01L2224/11005 , H01L2224/11009 , H01L2224/111 , H01L2224/11318 , H01L2224/11334 , H01L2224/1134 , H01L2224/11849 , H01L2224/11901 , H01L2224/1191 , H01L2224/13005 , H01L2224/13017 , H01L2224/13018 , H01L2224/13021 , H01L2224/13022 , H01L2224/13078 , H01L2224/1308 , H01L2224/13082 , H01L2224/13084 , H01L2224/131 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/1319 , H01L2224/13561 , H01L2224/13562 , H01L2224/136 , H01L2224/13609 , H01L2224/13611 , H01L2224/1405 , H01L2224/16058 , H01L2224/16059 , H01L2224/16145 , H01L2224/16147 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/1701 , H01L2224/1703 , H01L2224/17181 , H01L2224/17505 , H01L2224/2919 , H01L2224/73104 , H01L2224/73204 , H01L2224/75253 , H01L2224/81138 , H01L2224/81141 , H01L2224/81193 , H01L2224/81203 , H01L2224/8121 , H01L2224/8122 , H01L2224/81224 , H01L2224/81815 , H01L2224/81825 , H01L2224/8385 , H01L2224/9211 , H01L2225/06513 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15321 , H01L2924/3512 , H01L2924/381 , H01L2924/3841 , H05K1/115 , H05K1/144 , H05K3/341 , H05K2201/09572 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2924/07025 , H01L2224/81 , H01L2224/83

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

23.

发明申请
RELIABLE PACKAGING AND INTERCONNECT STRUCTURES 有权
Title translation: 可靠的包装和互连结构

公开(公告)号：US20160307798A1

公开(公告)日：2016-10-20

申请号：US15195641

申请日：2016-06-28

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH , Belgacem HABA , Craig MITCHELL

IPC: H01L21/768 , H01L23/532 , H01L23/48

CPC classification number: H01L23/528 , H01L21/2885 , H01L21/3212 , H01L21/76802 , H01L21/76804 , H01L21/76807 , H01L21/76831 , H01L21/76834 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76852 , H01L21/76868 , H01L21/76873 , H01L21/76879 , H01L21/76883 , H01L21/76885 , H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/53209 , H01L23/53238 , H01L24/13 , H01L24/14 , H01L2221/1094 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/13025 , H01L2224/13111 , H01L2224/14181 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552

Abstract: Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.

Abstract translation: 提供了用于形成半导体器件的方法和装置，其可以包括任何数量的特征。一个特征是形成互连结构的方法，其导致互连结构具有覆盖在不同材料中的互连结构的顶表面和侧壁的部分。在一些实施例中，异种材料可以是导电材料或纳米合金。互连结构可以通过去除互连结构的一部分并且用不同材料覆盖互连结构来形成。互连结构可以包括镶嵌结构，例如单镶嵌结构或双镶嵌结构，或者可以包括硅通孔（TSV）结构。

24.

发明申请
DEVICE AND METHOD FOR LOCALIZED UNDERFILL 有权

公开(公告)号：US20160042978A1

公开(公告)日：2016-02-11

申请号：US14453413

申请日：2014-08-06

Applicant: Invensas Corporation

Inventor： Liang WANG , Rajesh KATKAR , Charles G. WOYCHIK , Cyprian Emeka UZOH

IPC: H01L21/56 , H01L23/31 , H01L25/00 , H01L25/065

CPC classification number: H01L23/3178 , H01L21/4853 , H01L21/52 , H01L21/54 , H01L21/563 , H01L23/13 , H01L23/3157 , H01L23/49811 , H01L23/49827 , H01L23/49838 , H01L25/0655 , H01L25/50 , H01L2224/131 , H01L2224/16227 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2225/06517 , H01L2225/06555 , H01L2225/06593 , H01L2924/15153 , H01L2924/15156 , H01L2924/014

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.