公开(公告)号：US20160201198A1

公开(公告)日：2016-07-14

申请号：US14910633

申请日：2014-08-07

Applicant: LG CHEM, LTD

Inventor： Jae Hyun KIM ,  Eun Kyu SEONG ,  Su Jeong LEE ,  Jae Jin KIM ,  Cheol-Hee PARK ,  Chee-Sung PARK ,  Shin Hee JUN ,  Sang Yun JUNG ,  Han Nah JEONG

IPC: C23C18/31 ,  C23C18/16

CPC classification number: C23C18/31 ,  C09D5/24 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1641 ,  C23C18/1689 ,  C23C18/204 ,  C23C18/2053 ,  C23C18/2073 ,  C23C18/22 ,  C23C18/30 ,  C23C18/32 ,  C23C18/38 ,  C25D5/02 ,  C25D5/56 ,  H05K1/0296 ,  H05K1/09 ,  H05K3/02 ,  H05K3/181 ,  H05K2201/09009

Abstract: Provided are a method for forming conductive pattern by direct radiation of an electromagnetic wave capable of forming fine conductive patterns on various kinds of polymer resin products or resin layers under a relatively low power by a simplified process, even without containing specific inorganic additives in the polymer resin itself, and a resin structure having the conductive pattern formed thereon.The method for forming the conductive pattern by direct radiation of the electromagnetic wave includes: forming a first region having a predetermined surface roughness by selectively radiating the electromagnetic wave on a polymer resin substrate containing carbon-based black pigment; forming a conductive seed on the polymer resin substrate; forming a metal layer by plating the polymer resin substrate having the conductive seed formed thereon; and removing the conductive seed and the metal layer from a second region of the polymer resin substrate, wherein the second region has surface roughness smaller than that of the first region.

Abstract translation: 提供一种通过简单的方法在相对低功率下在各种聚合物树脂产品或树脂层上形成精细导电图案的电磁波的直接辐射来形成导电图案的方法，即使在聚合物中也不含有特定的无机添加剂 树脂本身以及其上形成有导电图案的树脂结构。 通过电磁波的直接辐射形成导电图案的方法包括：通过选择性地将电磁波辐射到包含碳黑色颜料的聚合物树脂基板上，形成具有预定表面粗糙度的第一区域; 在聚合物树脂基材上形成导电种子; 通过对其上形成有导电种子的聚合物树脂基板进行电镀而形成金属层; 以及从所述聚合物树脂基板的第二区域去除所述导电种子和所述金属层，其中所述第二区域的表面粗糙度小于所述第一区域的表面粗糙度。

公开(公告)号：US20150382478A1

公开(公告)日：2015-12-31

申请号：US14767536

申请日：2013-02-12

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： Hiroshi SHIMADA ,  Mitsuaki TODA ,  Tohru MATSUMOTO

IPC: H05K3/20 ,  C23F1/00 ,  H05K3/22 ,  H05K3/46 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/20 ,  C23F1/00 ,  H05K1/0298 ,  H05K1/185 ,  H05K1/188 ,  H05K3/22 ,  H05K3/4611 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09009 ,  H05K2201/10636 ,  H05K2203/11 ,  Y02P70/611

Abstract: A device embedded substrate includes an insulating layer including an insulating resin material, a device embedded in the insulating layer, a metal film coating at least one face of the device, and a roughened portion formed by roughening at least part of the surface of the metal film. Preferably, the device embedded substrate further includes: a conductive layer pattern-formed on a bottom face, the bottom face being one face of the insulating layer; and a bonding agent made of a material different from the insulating layer and joining the conductive layer (6) and a mounting face, the mounting face being one face of the device. The metal film is formed only on a face opposite to the mounting face, and the bonding agent has a thickness smaller than a thickness from the metal film to a top face, the top face being the other face of the insulating layer.

Abstract translation: 一种器件嵌入式衬底包括绝缘层，该绝缘层包括绝缘树脂材料，嵌入绝缘层中的器件，涂覆该器件的至少一个面的金属膜以及通过使金属的至少一部分表面粗糙化而形成的粗糙部分 电影。 优选地，装置嵌入式基板还包括：导电层图案形成在底面上，底面是绝缘层的一个面; 以及由与所述绝缘层不同的材料制成的接合剂，并且将所述导电层（6）和安装面接合，所述安装面是所述装置的一个面。 金属膜仅形成在与安装面相反的面上，粘合剂的厚度小于从金属膜到顶面的厚度，顶面是绝缘层的另一面。

公开(公告)号：US20140313683A1

公开(公告)日：2014-10-23

申请号：US14357450

申请日：2012-11-06

Applicant: LG INNOTEK CO., LTD.

Inventor： Hong Il Kim

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L21/486 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/181 ,  H05K3/0038 ,  H05K2201/09009 ,  H01L2924/00

Abstract: Provided are a tape carrier package and a method of manufacturing the same, the method, including: forming through holes by performing a drill process using a laser to an insulating film of a flexible copper clad laminate (FCCL) film consisting of the insulating film and a copper layer; forming a circuit pattern layer by performing an etching process to the copper layer of the FCCL film; and selectively forming a plating layer on the circuit pattern layer. The method of manufacturing the tape carrier package according to the present invention is advantageous because a punching process, and processes for laminating and drying the copper layer which are necessary for the conventional method of manufacturing the tape carrier package can be omitted, a production cost of the tape carrier package is reduced, and the time required for the drying process is saved.

Abstract translation: 提供一种载带封装及其制造方法，该方法包括：通过对由绝缘膜和由绝缘膜构成的柔性覆铜层压板（FCCL）膜的绝缘膜进行激光的钻孔处理来形成通孔， 铜层; 通过对FCCL膜的铜层进行蚀刻工艺形成电路图案层; 并且在电路图案层上选择性地形成镀层。 根据本发明的带状载体包装的制造方法是有利的，因为可以省略传统的制造带状载体包装方法所需的冲压工艺和层压和干燥铜层的方法，生产成本 减少了载带包装，节省了干燥过程所需的时间。

公开(公告)号：US11664567B2

公开(公告)日：2023-05-30

申请号：US17106269

申请日：2020-11-30

Applicant: NXP B.V.

Inventor： Adrianus Buijsman ,  Abdellatif Zanati ,  Giorgio Carluccio

IPC: H01P3/12 ,  H01P11/00 ,  H01L23/66 ,  H01P5/107 ,  H01Q1/32 ,  H01Q1/38 ,  H05K3/46

CPC classification number: H01P3/12 ,  H01L23/66 ,  H01P3/121 ,  H01P5/107 ,  H01P11/002 ,  H01Q1/3233 ,  H01Q1/38 ,  H05K3/4697 ,  H01L2223/6627 ,  H05K2201/037 ,  H05K2201/09009

Abstract: A method of manufacturing a device is provided. The method includes forming a first cavity in a first substrate with the first cavity having a first depth. A second cavity is formed in a second substrate with the second cavity having a second depth. The first cavity and the second cavity are aligned with each other. The first substrate is affixed to the second substrate to form a waveguide substrate having a hollow waveguide with a first dimension substantially equal to the first depth plus the second depth. A conductive layer is formed on the sidewalls of the hollow waveguide. The waveguide substrate is placed over a packaged semiconductor device, the hollow waveguide aligned with a launcher of the packaged semiconductor device.

公开(公告)号：US20180356083A1

公开(公告)日：2018-12-13

申请号：US15859409

申请日：2017-12-30

Applicant: Fluence Bioengineering

Inventor： Dung Duong ,  Randy Johnson ,  Nick Klase

IPC: F21V23/00 ,  H05K1/05 ,  H05K1/18 ,  H05K1/02 ,  H05K3/32 ,  F21V29/74 ,  F21K9/90

CPC classification number: F21V29/70 ,  A01G7/045 ,  F21K9/232 ,  F21K9/90 ,  F21S4/28 ,  F21V7/005 ,  F21V7/0066 ,  F21V7/05 ,  F21V15/015 ,  F21V17/107 ,  F21V19/0015 ,  F21V19/003 ,  F21V23/001 ,  F21V23/005 ,  F21V23/02 ,  F21V29/74 ,  F21V29/83 ,  F21Y2103/10 ,  F21Y2105/16 ,  F21Y2115/10 ,  H05B33/0854 ,  H05B37/0272 ,  H05K1/0203 ,  H05K1/0274 ,  H05K1/0277 ,  H05K1/05 ,  H05K1/181 ,  H05K1/182 ,  H05K1/185 ,  H05K3/0014 ,  H05K3/28 ,  H05K3/32 ,  H05K3/44 ,  H05K2201/066 ,  H05K2201/09009 ,  H05K2201/10106

Abstract: Examples of the present disclosure are related to systems and methods for lighting fixtures. More particularly, embodiments disclose directly embedded a smart module with a lighting fixture utilizing metal core PCB (MCPCB).

公开(公告)号：US20180324949A1

公开(公告)日：2018-11-08

申请号：US15970893

申请日：2018-05-04

Applicant: CYNTEC CO., LTD.

Inventor： Chi-Feng Huang

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/42 ,  H05K1/09 ,  H05K1/14

CPC classification number: H05K1/117 ,  H05K1/09 ,  H05K1/115 ,  H05K1/14 ,  H05K1/185 ,  H05K3/423 ,  H05K2201/09009 ,  H05K2201/1003 ,  H05K2201/10378

Abstract: An electronic module is disclosed, wherein the electronic module comprises: a first circuit board, comprising a top surface, a bottom surface, and a lateral surface connecting the top surface and the bottom surface of the first circuit board; wherein an electrode structure is disposed on the first circuit board, wherein a second circuit board is disposed under the bottom surface of the first circuit board, wherein a soldering material is disposed between the bottom surface of the electrode structure and the second circuit board and extended onto a wettable flank of the electrode structure to form a soldering structure, wherein said soldering structure comprises an outer surface that is located above the bottom surface of the first circuit board and outside the outmost portion of the lateral surface of the first circuit board.

公开(公告)号：US20180063957A1

公开(公告)日：2018-03-01

申请号：US15556700

申请日：2016-03-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Hisashi WATANABE

IPC: H05K1/14 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02 ,  G02F1/1345

CPC classification number: H05K1/147 ,  G02F1/133615 ,  G02F1/13452 ,  G02F2201/56 ,  H05K1/028 ,  H05K1/118 ,  H05K1/148 ,  H05K1/189 ,  H05K2201/055 ,  H05K2201/056 ,  H05K2201/09009 ,  H05K2201/09027 ,  H05K2201/10128 ,  H05K2201/10136

Abstract: The present invention provides a flexible printed circuit capable of being mounted to an outer edge portion of a display panel including a periphery that is at least partially curved. The flexible printed circuit of the present invention includes: a flexible substrate provided with multiple slits; multiple conductive lines; and multiple terminals electrically coupled with the respective conductive lines in an independent manner. The slits and the conductive lines are disposed in the longitudinal direction of the flexible substrate. The terminals are disposed on a first longitudinal end of the flexible substrate.

公开(公告)号：US09894763B2

公开(公告)日：2018-02-13

申请号：US14827456

申请日：2015-08-17

Applicant: NGK INSULATORS, LTD.

Inventor： Tatsuro Takagaki ,  Yasunori Iwasaki ,  Sugio Miyazawa ,  Akiyoshi Ide ,  Hirokazu Nakanishi

IPC: H05K1/03 ,  H05K1/11 ,  C04B35/119 ,  H01B3/12 ,  C04B35/111 ,  H05K3/00 ,  H01B17/56 ,  C04B35/634

CPC classification number: H05K1/115 ,  C04B35/111 ,  C04B35/119 ,  C04B35/634 ,  C04B2235/3206 ,  C04B2235/3217 ,  C04B2235/3225 ,  C04B2235/3244 ,  C04B2235/3281 ,  C04B2235/3418 ,  C04B2235/6023 ,  C04B2235/606 ,  C04B2235/612 ,  C04B2235/6582 ,  C04B2235/662 ,  C04B2235/72 ,  C04B2235/77 ,  C04B2235/786 ,  C04B2235/95 ,  H01B3/12 ,  H01B17/56 ,  H05K1/03 ,  H05K1/0306 ,  H05K3/00 ,  H05K3/0014 ,  H05K3/0029 ,  H05K2201/09009 ,  Y10T428/24273

Abstract: It is provided an insulating substrate including through holes 2 for conductors arranged in the insulating substrate. A thickness of the insulating substrate is 25 to 300 μm , and a diameter of the through hole is 20 to 100 μm . The insulating substrate is composed of an alumina sintered body. A relative density and an average grain size of the alumina sintered body is 99.5 percent or higher and 2 to 50 μm , respectively.

公开(公告)号：US20180042124A1

公开(公告)日：2018-02-08

申请号：US15671451

申请日：2017-08-08

Applicant: IBIDEN CO., LTD.

Inventor： Toshihide MAKINO ,  Hidetoshi Noguchi

IPC: H05K3/46 ,  H05K1/16 ,  H05K3/20

CPC classification number: H05K3/4652 ,  H05K1/0366 ,  H05K1/11 ,  H05K1/111 ,  H05K1/115 ,  H05K1/116 ,  H05K1/16 ,  H05K3/061 ,  H05K3/202 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/09009 ,  H05K2201/096

Abstract: A wiring board includes core substrate, a first build-up layer on first surface of the substrate and including conductive and insulating resin layers, and a second build-up layer on second surface of the substrate and including conductive and insulating resin layers. The first build-up is formed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer, and the second build-up is foimed such that each conductive layer includes a metal foil layer and a plating layer on the foil layer and the foil layer of a conductive layer on an outermost resin layer has thickness greater than thickness of the foil layer of each conductive layer on a non-outermost resin layer.

公开(公告)号：US09888558B2

公开(公告)日：2018-02-06

申请号：US13152419

申请日：2011-06-03

Applicant: Akira Harao ,  Mototatsu Matsunaga ,  Yasuhiro Sugiura ,  Minoru Kubota

Inventor： Akira Harao ,  Mototatsu Matsunaga ,  Yasuhiro Sugiura ,  Minoru Kubota

IPC: H05K1/03 ,  H05K1/02 ,  H01R12/72 ,  H05K3/36 ,  H05K1/11 ,  H05K3/10 ,  H01L23/498 ,  H05K7/10 ,  H05K1/05 ,  H05K3/20 ,  H05K3/34 ,  H05K1/14

CPC classification number: H05K1/0204 ,  H01L23/49861 ,  H01L2224/05571 ,  H01L2224/48091 ,  H01L2225/1094 ,  H01R12/728 ,  H05K1/0203 ,  H05K1/05 ,  H05K1/056 ,  H05K1/11 ,  H05K1/14 ,  H05K3/10 ,  H05K3/202 ,  H05K3/3447 ,  H05K3/368 ,  H05K7/1046 ,  H05K2201/09009 ,  H05K2201/09063 ,  H05K2201/10757 ,  H05K2201/10787 ,  H05K2203/025 ,  Y10T29/49147 ,  Y10T29/49155

Abstract: A wiring substrate 11A includes a high heat radiation substrate 21 which has a high thermal conductive layer in which at least one of a front surface and a rear surface thereof is a mounting surface 21a for a variety of components; a connection terminal 31 which is extended from the high heat radiation substrate 21 and bent in a direction perpendicular to a surface of the high heat radiation substrate 21; and a heat radiation piece section 35 which is integrally installed to the connection terminal 31.