公开(公告)号：US20190200449A1

公开(公告)日：2019-06-27

申请号：US16174665

申请日：2018-10-30

Applicant: Japan Aviation Electronics Industry, Limited

Inventor： Kentaro TODA

IPC: H05K1/02

CPC classification number: H05K1/0222 ,  H01R12/53 ,  H01R12/722 ,  H05K1/0228 ,  H05K2201/09027 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09272 ,  H05K2201/09618

Abstract: A circuit board comprises at least a first wiring layer, a second wiring layer and a via. The first wiring layer is formed with a pair of first ends, a pair of second ends, a coupling portion, a pair of first trace portions and a pair of second trace portions. The coupling portion has a pair of first coupling points, a pair of second coupling points, an inner trace portion, an outer trace portion and a ground conductor portion. The inner trace portion has a length equal to a length of the outer trace portion. The ground conductor portion is arranged between the inner trace portion and the outer trace portion. The second wiring layer is formed with a ground pattern. The ground conductor portion is connected with the ground pattern through the via.

公开(公告)号：US20190098855A1

公开(公告)日：2019-04-04

申请号：US16192673

申请日：2018-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsushi Morishima

IPC: A01H5/10 ,  C12N15/82 ,  A01H6/54 ,  A01H1/02

CPC classification number: A01H5/10 ,  A01H1/02 ,  A01H6/542 ,  C12N15/8245 ,  C12N15/8247 ,  C12N15/8251 ,  C12N15/8271 ,  C12N15/8274 ,  C12N15/8275 ,  C12N15/8278 ,  C12N15/8279 ,  C12N15/8286 ,  C12N15/8289 ,  H05K1/025 ,  H05K1/114 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US20190075653A1

公开(公告)日：2019-03-07

申请号：US15696102

申请日：2017-09-05

Applicant: Apple Inc.

Inventor： Mark J. Beesley ,  Albert A. Onderick, II ,  Anne M. Mason ,  Craig A. Gammel ,  Shawn X. Arnold

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/00

CPC classification number: H05K1/112 ,  H05K1/11 ,  H05K1/114 ,  H05K1/115 ,  H05K1/14 ,  H05K3/0017 ,  H05K3/0047 ,  H05K3/3436 ,  H05K3/425 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/10734

Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

公开(公告)号：US20180299929A1

公开(公告)日：2018-10-18

申请号：US15948799

申请日：2018-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Soo KIM ,  Kyujin KWAK ,  Soo-Gyu LEE ,  Sung-Won PARK ,  Joon Won CHANG ,  Jin-Wan AN ,  Janghoon LEE

IPC: G06F1/16 ,  H05K1/02 ,  H05K7/14 ,  H05K5/03 ,  H05K1/18

CPC classification number: G06F1/1658 ,  G06F1/1626 ,  G06F1/1635 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1656 ,  G06F1/1698 ,  G06F1/20 ,  G06F1/203 ,  G06F2203/04105 ,  H01Q1/243 ,  H02J7/0052 ,  H04M1/0277 ,  H05K1/028 ,  H05K1/05 ,  H05K1/144 ,  H05K1/148 ,  H05K1/181 ,  H05K5/03 ,  H05K7/1427 ,  H05K2201/0311 ,  H05K2201/042 ,  H05K2201/09227 ,  H05K2201/10166

Abstract: An electronic device is provided. The electronic device includes a housing comprising a first plate, a second plate apart from the first plate while facing the first plate, and a side member which surrounds a space between the first plate and the second plate, a touchscreen display exposed through the first plate, a printed circuit board (PCB) disposed between the touchscreen display and the second plate, a mid-plate disposed between the touchscreen display and the PCB, and extending from the side member, and at least one integrated circuit (IC) mounted on the PCB and relating to power, wherein the mid-plate can include at least one conductive path formed on a surface facing the PCB and electrically connected to the at least one IC, and the at least one conductive path can be formed with the same metallic material as the mid-plate.

公开(公告)号：US20180279464A1

公开(公告)日：2018-09-27

申请号：US15993635

申请日：2018-05-31

Applicant: Guangdong Oppo Mobile Telecommunications Corp., Ltd.

Inventor： Yan Chen

IPC: H05K1/02

CPC classification number: H05K1/025 ,  H05K1/0219 ,  H05K1/0245 ,  H05K1/028 ,  H05K1/0393 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09336

Abstract: A flexible printed circuit (FPC) wiring structure and a mobile terminal are provided. The FPC wiring structure includes an FPC body. The FPC body is a single-layer board. The FPC body includes a substrate layer and a signal line, a first wire, and a second wire arranged on the substrate layer. The signal line includes a first wiring area disposed on one side of the signal line and a second wiring area disposed on the other side of the signal line. The first wire is arranged in the first wiring area and the second wire is arranged in the second wiring area. A distance between the first wire and the signal line is equal to that between the second wire and the signal line.

公开(公告)号：US20180242912A1

公开(公告)日：2018-08-30

申请号：US15756410

申请日：2016-08-31

Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY

Inventor： Ichiro AMIMORI ,  Masao NAKAJIMA ,  Takao SOMEYA

IPC: A61B5/00 ,  A41D1/00 ,  A61B5/11 ,  H05K1/11 ,  H05K1/18 ,  H05K1/03

CPC classification number: A61B5/6804 ,  A41D1/005 ,  A61B5/0024 ,  A61B5/11 ,  A61B5/7267 ,  A61B2562/046 ,  A61B2562/164 ,  A61B2562/166 ,  A61B2562/222 ,  A61B2562/227 ,  H04Q9/00 ,  H05K1/038 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/09445 ,  H05K2201/10151

Abstract: A connector substrate includes a base material, n first input terminals of m groups (m and n are an integer equal to or greater than 2) which are provided on the base material, n first output terminals which are provided on the base material, first wiring patterns which are disposed on or inside the base material and connect the first input terminals and the first output terminals, m second input terminals which are provided on the base material, m second output terminals which are provided on the base material, and second wiring patterns which are disposed on or inside the base material and connect the second input terminals and the second output terminals, in which a first end of each connector wiring constituting the first wiring pattern is connected to one of the n first input terminals constituting each group, and a second end is connected to one of the first output terminals.

公开(公告)号：US10043960B2

公开(公告)日：2018-08-07

申请号：US13296812

申请日：2011-11-15

Applicant: Peter Scott Andrews ,  Jeffrey Carl Britt

Inventor： Peter Scott Andrews ,  Jeffrey Carl Britt

IPC: H01L33/08 ,  H01L33/38 ,  H01L33/62 ,  H01L33/60 ,  H01L33/20 ,  H01L25/075 ,  H01L33/64 ,  H01L23/373 ,  H05K1/03 ,  H05K1/02 ,  H05K3/06 ,  H05K3/16

CPC classification number: H01L33/62 ,  H01L23/3735 ,  H01L25/0753 ,  H01L33/60 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/12032 ,  H05K1/0269 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/16 ,  H05K2201/0338 ,  H05K2201/09036 ,  H05K2201/09227 ,  H05K2201/10106 ,  H05K2201/2054 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Light emitting diode (LED) packages and methods are disclosed herein. In one aspect, a light emitting package is disclosed. The light emitting package includes one or more areas of conductive material having a thickness of less than approximately 50 microns (μm). The package can further include at least one light emitting diode (LED) electrically connected to the conductive material and at least one thin gap disposed between areas of conductive material.

公开(公告)号：US09986634B2

公开(公告)日：2018-05-29

申请号：US15381301

申请日：2016-12-16

Applicant: Curtiss-Wright Controls, Inc.

Inventor： Michael Rose ,  Robert Sullivan

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/20 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0216 ,  H05K1/024 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/20 ,  H05K3/4038 ,  H05K2201/0187 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/1059

Abstract: A circuit board comprises a plurality of layers, first and second reference conductive vias extending in a vertical direction through at least a portion of the plurality of layers, first and second signal conductive vias extending in the vertical direction between and spaced apart in a horizontal direction from the first and second reference conductive vias through at least a portion of the plurality of layers, and a dielectric region extending in the vertical direction between the first and second signal conductive vias. An air via extends in the vertical direction through the dielectric region between the first and second signal conductive vias. An anti-pad extends in the horizontal direction between the first and second reference conductive vias and surrounding in the horizontal direction the first and second signal conductive vias, the air via, and the dielectric region.

公开(公告)号：US09978515B2

公开(公告)日：2018-05-22

申请号：US14568446

申请日：2014-12-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuto Ogawa ,  Isao Kato

IPC: H05K7/00 ,  H05K1/16 ,  H01G2/06 ,  H05K1/11 ,  H01G4/12 ,  H01G4/30 ,  H05K1/18 ,  H05K3/30 ,  H05K3/00

CPC classification number: H01G2/065 ,  H01G2/06 ,  H01G4/12 ,  H01G4/30 ,  H05K1/111 ,  H05K1/181 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/303 ,  H05K2201/09063 ,  H05K2201/09227 ,  H05K2201/10015 ,  H05K2201/2045 ,  Y02P70/611 ,  Y10T29/4913

Abstract: An electronic component unit includes a substrate including principal surfaces opposing each other and side surfaces between the principal surfaces, and components mounted on the principal surface of the substrate. The side surfaces include first side surfaces formed before the components are mounted and second side surfaces formed after the components are mounted. As viewed from a line normal to the principal surface of the substrate, distances between the first side surfaces and the components are different from distances between the second side surfaces and the components.

公开(公告)号：US20180116051A1

公开(公告)日：2018-04-26

申请号：US15847852

申请日：2017-12-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.