公开(公告)号：US20090269286A1

公开(公告)日：2009-10-29

申请号：US12111503

申请日：2008-04-29

申请人： George F. Walker

发明人： George F. Walker

IPC分类号： A61K9/44

CPC分类号： A61K9/2072 ,  A61J3/007 ,  A61J2200/20 ,  A61J2205/10 ,  A61J2205/20 ,  A61J2205/40 ,  A61J2205/50

摘要： The invention is an article of manufacture, comprising an identifying marker disposed in a pharmaceutical product. The pharmaceutical product may be selected from the group consisting of a pharmaceutical liquid, a pill, a tablet, a caplet, and a capsule. The identifying marker may be a hydroscopic medium having an indicia imprinted thereon or within, where the marker expands volumetrically when contacted with a liquid.

摘要翻译： 本发明是一种制品，其包括设置在药品中的识别标记。 药物产品可以选自药物液体，丸剂，片剂，囊片和胶囊。 识别标记物可以是具有印记在其上或内部的标记的吸湿介质，其中当与液体接触时，标记物在体积上膨胀。

公开(公告)号：US07273806B2

公开(公告)日：2007-09-25

申请号：US10905013

申请日：2004-12-09

申请人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： Robert A. Groves ,  Peter A. Gruber ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L21/44

CPC分类号： H05K3/3468 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/4853 ,  H01L21/6835 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01058 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K3/325 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K2203/162 ,  H05K2203/167 ,  H01L2224/0401

摘要： Methods of forming a conductive structure on a substrate prior to packaging, and a test probe structure generated according to the method, are disclosed. The conductive structure includes a high aspect ratio structure formed by injected molded solder. The invention can be applied to form passive elements and interconnects on a conventional semiconductor substrate after the typical BEOL, and prior to packaging. The method may provide better electromigration characteristics, lower resistivity, and higher Q factors for conductive structures. In addition, the method is backwardly compatible and customizable.

摘要翻译： 公开了在封装之前在基板上形成导电结构的方法和根据该方法生成的测试探针结构。 导电结构包括通过注射成型的焊料形成的高纵横比结构。 本发明可以应用于在典型的BEOL之后以及在封装之前在常规半导体衬底上形成无源元件和互连。 该方法可以为导电结构提供更好的电迁移特性，较低的电阻率和更高的Q因子。 此外，该方法可以向后兼容并可定制。

公开(公告)号：US07252514B2

公开(公告)日：2007-08-07

申请号：US10931428

申请日：2004-09-02

申请人： Samuel R. McKnight ,  George F. Walker

发明人： Samuel R. McKnight ,  George F. Walker

IPC分类号： H01R12/00 ,  H05K1/00

CPC分类号： H01R9/0515 ,  G01R1/06772 ,  G01R1/07378

摘要： A method for forming a space transformer (and a space transformer formed by the method) having a first plate and a second plate, the plates being separated by a frame, and electrical connectors for providing electrical connections between electrical contacts which are relatively closely spaced on the first plate and relatively more widely spaced on the second plate. The method comprises attaching first ends of wires to first electrically conductive regions on the first plate; forming insulating layers over the wires; forming electrically conductive coverings over the insulating layers; and connecting second ends of the wires to second electrically conductive regions on the second plate.

摘要翻译： 一种用于形成具有第一板和第二板的空间变压器（和由该方法形成的空间变压器）的方法，所述板由框架分隔开，并且电连接器用于在电触点之间提供电连接，所述电触点相对紧密地间隔开 第一板并且在第二板上相对更宽的间隔。 该方法包括将导线的第一端附接到第一板上的第一导电区域; 在导线上形成绝缘层; 在绝缘层上形成导电覆盖物; 并且将所述导线的第二端连接到所述第二板上的第二导电区域。

公开(公告)号：US06656750B1

公开(公告)日：2003-12-02

申请号：US09301889

申请日：1999-04-29

申请人： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

发明人： Madhav Datta ,  Peter A. Gruber ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  George F. Walker

IPC分类号： G01R3126

CPC分类号： H01L24/13 ,  B23K1/0016 ,  B23K1/20 ,  B23K2101/36 ,  G01R31/2886 ,  H01L22/00 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1148 ,  H01L2224/1184 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H01L2924/00014

摘要： A method for testing integrated circuit chips with probe wires on flat solder bumps and IC chips that are equipped with flat solder bumps are disclosed. In the method, an IC chip that has a multiplicity of bond pads and a multiplicity of flat solder bumps are first provided in which each of the solder bumps has a height less than ½ of its diameter on the multiplicity of bond pads. The probe wires can thus be easily used to contact the increased target area on the solder bumps for establishing electrical connection with a test circuit. The probe can further be conducted easily with all the Z height of the bumps are substantially equal. The height of the solder bumps may be suitably controlled by either a planarization process in which soft solder bumps are compressed by a planar surface, or solder bumps are formed in an in-situ mold by either a MSS or an electroplating process for forming solder bumps in the shape of short cylinders. When the MSS method is used for planting the bumps, solder bumps are transferred onto the wafer surface in a substantially flattened hemi-spherical shape.

摘要翻译： 公开了一种在平坦焊料凸块上测试集成电路芯片的方法以及配备有平坦焊料凸块的IC芯片。 在该方法中，首先提供具有多个接合焊盘和多个平坦焊料凸块的IC芯片，其中每个焊料凸块在多个焊盘上具有小于其直径的1/2的高度。 因此，探针线可以容易地用于接触焊料凸块上的增加的目标区域，以建立与测试电路的电连接。 探针可以容易地进行，凸块的所有Z高度基本相等。 焊料凸块的高度可以通过平面化处理来适当地控制，其中软焊料凸块被平面表面压缩，或者通过用于形成焊料凸块的MSS或电镀工艺在原位模具中形成焊料凸块 呈短圆柱形。 当使用MSS方法种植凸块时，焊料凸块以大致平坦的半球形转移到晶片表面上。

公开(公告)号：US06534863B2

公开(公告)日：2003-03-18

申请号：US09781121

申请日：2001-02-09

申请人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

发明人： George F. Walker ,  Ronald D. Goldblatt ,  Peter A. Gruber ,  Raymond R. Horton ,  Kevin S. Petrarca ,  Richard P. Volant ,  Tien-Jen Cheng

IPC分类号： H01L2348

CPC分类号： H01L24/48 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05083 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05169 ,  H01L2224/05181 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00015 ,  H01L2924/00012

摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

公开(公告)号：US06339024B1

公开(公告)日：2002-01-15

申请号：US09605728

申请日：2000-06-28

申请人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

发明人： Kevin S. Petrarca ,  John E. Heidenreich, III ,  Judith M. Rubino ,  Carlos J. Sambucetti ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L2044

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14

摘要： A method of manufacturing integrated circuits wherein a conductive structure in a topmost semiconductive layer of an integrated circuit is provided having a thickness greater than or equal to 1.5 &mgr;m. The thickness of the conductive structure is sufficiently great as to effectively protect any layers beneath the topmost semiconductive layer from damage from pressure, such as pressure applied by testing probes. In a preferred embodiment, traditional aluminum TD leveling is discarded in favor of gold deposited upon the thickened conductive layer.

摘要翻译： 一种制造集成电路的方法，其中提供具有大于或等于1.5μm厚度的集成电路的最上半导体层中的导电结构。 导电结构的厚度足够大，以有效地保护最高半导体层下面的任何层免受来自压力（例如由测试探针施加的压力）的损害。 在优选的实施方案中，传统的铝TD匀染被丢弃，有利于沉积在增厚的导电层上的金。

公开(公告)号：US5633047A

公开(公告)日：1997-05-27

申请号：US449196

申请日：1995-05-24

申请人： Michael J. Brady ,  Curtis E. Farrell ,  Sung K. Kang ,  Jeffrey R. Marino ,  Donald J. Mikalsen ,  Paul A. Moskowitz ,  Eugene J. O'Sullivan ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  Sheldon C. Rieley ,  George F. Walker

发明人： Michael J. Brady ,  Curtis E. Farrell ,  Sung K. Kang ,  Jeffrey R. Marino ,  Donald J. Mikalsen ,  Paul A. Moskowitz ,  Eugene J. O'Sullivan ,  Terrence R. O'Toole ,  Sampath Purushothaman ,  Sheldon C. Rieley ,  George F. Walker

IPC分类号： C23C18/50 ,  C25D3/54 ,  H01L23/495 ,  H01L23/532 ,  B05D1/18

CPC分类号： H01L24/12 ,  C23C18/50 ,  C25D3/54 ,  H01L23/4951 ,  H01L23/53271 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/73215 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85214 ,  H01L24/45 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181

摘要： Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

摘要翻译： 在电子设备中的导体的表面使用含锗和锗的材料。 焊料可无焊接，电线可以与这些表面引线接合。 这些材料用作用于封装集成电路芯片的引线框架的表面涂层。 这些材料可以贴花地转移到导体表面上，或者无电解或电解地放置在其上。

公开(公告)号：US5600257A

公开(公告)日：1997-02-04

申请号：US513057

申请日：1995-08-09

申请人： James M. Leas ,  Robert W. Koss ,  George F. Walker ,  Charles H. Perry ,  Jody J. Van Horn

发明人： James M. Leas ,  Robert W. Koss ,  George F. Walker ,  Charles H. Perry ,  Jody J. Van Horn

IPC分类号： G01R1/06 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R1/02

CPC分类号： G01R1/07385 ,  G01R1/07314 ,  G01R31/2889 ,  G01R31/2863 ,  G01R31/2879 ,  G01R31/2886

摘要： An apparatus and a method for simultaneously testing or burning in all the integrated circuit chips on a product wafer. The apparatus comprises a glass ceramic carrier having test chips and means for connection to pads of a large number of chips on a product wafer. Voltage regulators on the test chips provide an interface between a power supply and power pads on the product chips, at least one voltage regulator for each product chip. The voltage regulators provide a specified Vdd voltage to the product chips, whereby the Vdd voltage is substantially independent of current drawn by the product chips. The voltage regulators or other electronic means limit current to any product chip if it has a short. The voltage regulator circuit may be gated and variable and it may have sensor lines extending to the product chip. The test chips can also provide test functions such as test patterns and registers for storing test results.

摘要翻译： 用于在产品晶片上的所有集成电路芯片中同时测试或燃烧的装置和方法。 该装置包括具有测试芯片的玻璃陶瓷载体和用于连接到产品晶片上的大量芯片的焊盘的装置。 测试芯片上的电压调节器提供电源和产品芯片上的电源接口之间的接口，每个产品芯片至少有一个电压调节器。 电压调节器向产品芯片提供指定的Vdd电压，由此Vdd电压基本上与产品芯片所消耗的电流无关。 电压调节器或其他电子装置将电流限制在任何产品芯片上。 电压调节器电路可以是门控和可变的，并且其可以具有延伸到产品芯片的传感器线路。 测试芯片还可以提供测试功能，例如测试模式和用于存储测试结果的寄存器。

公开(公告)号：US5299939A

公开(公告)日：1994-04-05

申请号：US847970

申请日：1992-03-05

申请人： George F. Walker ,  Arthur Zingher

发明人： George F. Walker ,  Arthur Zingher

IPC分类号： H01R13/24 ,  H01R12/71 ,  H01R13/33 ,  H01R24/00 ,  H01R9/09

CPC分类号： H01R13/33 ,  H01R12/57 ,  H01R12/714 ,  H01R13/24

摘要： A spring array connector includes a unitary resilient layer of multiple springs having a layer of multiple electrically conducting lines, electrical contacts and electrical terminals. Each spring of the array is independently bendable and each of the conducting lines is electrically isolated from the other conducting lines. All of the springs in the spring array are fabricated simultaneously. Spring embodiments include sine, helix, cantilever and buckling beam shapes in sheet and wire forms.

摘要翻译： 弹簧阵列连接器包括具有多个导电线，电触头和电端子层的多个弹簧的单一弹性层。 阵列的每个弹簧都是可独立弯曲的，并且每条导线与其它导线电隔离。 弹簧阵列中的所有弹簧都是同时制造的。 弹簧实施例包括片材和线材形式的正弦，螺旋，悬臂和屈曲梁形状。

公开(公告)号：US5283104A

公开(公告)日：1994-02-01

申请号：US672272

申请日：1991-03-20

申请人： Farid Y. Aoude ,  Emanuel I. Cooper ,  Peter R. Duncombe ,  Shaji Farooq ,  Edward A. Giess ,  Young-Ho Kim ,  Sarah H. Knickerbocker ,  Friedel Muller-Landau ,  Mark O. Neisser ,  Jae M. Park ,  Robert R. Shaw ,  Robert A. Rita ,  Thomas M. Shaw ,  Rao Vallabhaneni ,  Jon A. Van Hise ,  George F. Walker ,  Jungihl Kim ,  James M. Brownlow, deceased

发明人： Farid Y. Aoude ,  Emanuel I. Cooper ,  Peter R. Duncombe ,  Shaji Farooq ,  Edward A. Giess ,  Young-Ho Kim ,  Sarah H. Knickerbocker ,  Friedel Muller-Landau ,  Mark O. Neisser ,  Jae M. Park ,  Robert R. Shaw ,  Robert A. Rita ,  Thomas M. Shaw ,  Rao Vallabhaneni ,  Jon A. Van Hise ,  George F. Walker ,  Jungihl Kim ,  James M. Brownlow, deceased

IPC分类号： H01B1/16 ,  H01L21/48 ,  H01L23/498 ,  H05K1/03 ,  H05K1/09 ,  H05K3/46 ,  B32B9/00

CPC分类号： H05K1/092 ,  H01B1/16 ,  H01L21/486 ,  H01L21/4867 ,  H01L23/49883 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/4611 ,  H05K3/4629 ,  Y10S428/901 ,  Y10T29/49147 ,  Y10T29/49165 ,  Y10T428/12472 ,  Y10T428/12556 ,  Y10T428/12604 ,  Y10T428/12611 ,  Y10T428/24322 ,  Y10T428/24802 ,  Y10T428/25 ,  Y10T428/251 ,  Y10T428/252 ,  Y10T428/2982 ,  Y10T428/2991

摘要： Improved via-filling compositions for producing conductive vias in circuitized ceramic substrates, particularly multilayer substrates, without cracking and/or loss of hermetic sealing. The via-filling compositions comprise pastes containing a mixture of (a) ceramic and/or glass spheres of substantially- uniform diameter between about 0.5 and 6 .mu.m, (b) conductive metal particles or spheres having a maximum dimension or diameter between about 1/3 and 1/4 of the diameter of the ceramic and/or glass spheres, and (c) a binder vehicle. The formed conductive via bodies comprise a uniform conductive skeletal network of sintered metal particles densely packed within a uniform matrix of the co-sintered ceramic and/or glass spheres, which matrix is hermetically fused and integrated with ceramic layers forming the wall of the via in the ceramic circuit substrate.

摘要翻译： 用于在电路化陶瓷衬底，特别是多层衬底中产生导电通孔的改进的通孔填充组合物，不会破裂和/或失去气密密封。 通孔填充组合物包含含有（a）在约0.5和6（my）m之间的基本均匀直径的陶瓷和/或玻璃球的混合物的浆料，（b）具有最大尺寸或直径在 约为陶瓷和/或玻璃球直径的1/3和1/4，和（c）粘合剂载体。 形成的导电通孔体包括致密地包裹在共烧结陶瓷和/或玻璃球的均匀基质内的烧结金属颗粒的均匀导电骨架网络，该基质被气密地融合并与形成通孔壁的陶瓷层成一体 陶瓷电路基板。