公开(公告)号：US09125332B2

公开(公告)日：2015-09-01

申请号：US12813335

申请日：2010-06-10

申请人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

发明人： Rajendra D. Pendse ,  Youngcheol Kim ,  TaeKeun Lee ,  GuiChea Na ,  GwangJin Kim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H05K3/34 ,  H01L23/00 ,  H05K3/00

CPC分类号： H05K3/3452 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0332 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16013 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/30105 ,  H05K3/0005 ,  H05K3/3436 ,  H05K2201/0989 ,  H05K2201/10734 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/81805

摘要： A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

摘要翻译： 半导体封装包括具有形成在凸块焊盘上的多个焊料凸块的半导体管芯。 衬底具有多个具有暴露侧壁的接触焊盘。 阻焊剂设置在每个接触垫的至少一部分上方开口。 焊料凸块被回流到冶金和电连接到接触焊盘。 每个接触垫的大小根据由SRO + 2 * SRR-2X定义的设计规则，其中SRO是阻焊剂开口，SRR是制造工艺的焊料对准，X是暴露侧壁的厚度的函数 的接触垫。 X的值范围为5至20微米。 焊料凸块润湿接触焊盘的暴露的侧壁并且基本上填充与暴露的侧壁相邻的区域。 接触垫可以制成圆形，矩形或圆环状。

公开(公告)号：US08987014B2

公开(公告)日：2015-03-24

申请号：US12467094

申请日：2009-05-15

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L21/66 ,  H01L23/31

CPC分类号： H01L22/32 ,  H01L23/3128 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

摘要： A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.

摘要翻译： 半导体晶片包含多个半导体管芯。 在半导体管芯上形成多个互连凸点焊盘。 多个牺牲凸块焊盘形成在相对于互连凸块焊盘附近并对角地偏移。 牺牲凸块具有与互连凸块焊盘不同的直径。 在每个互连凸块焊盘和邻近的牺牲凸块焊盘之间形成导电连接。 牺牲凸块，互连凸点焊盘和导电连接件同时或在凸块形成期间形成。 通过接触牺牲凸块来对晶片进行电测试。 电气测试识别已知的好模具和有缺陷的模具。 在晶圆探测之后，去除牺牲凸块和导电连接件的一部分。 在互连凸点焊盘上形成凸起。 半导体晶片可以在没有颠簸的晶圆探测之后出售或转移到第三方。

公开(公告)号：US08941235B2

公开(公告)日：2015-01-27

申请号：US13423262

申请日：2012-03-18

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/34 ,  H01L23/488 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H05K1/18 ,  H05K1/14

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81194 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/8383 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H05K1/141 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a first substrate with a central region. A plurality of bumps is formed around a periphery of the central region of the first substrate. A first semiconductor die is mounted to the central region of the first substrate. A second semiconductor die is mounted to the first semiconductor die over the central region of the first substrate. A height of the first and second die is less than or equal to a height of the bumps. A second substrate has a thermal conduction channel. A surface of the second semiconductor die opposite the first die is mounted to the thermal conductive channel of the second substrate. A thermal interface layer is formed over the surface of the second die. The bumps are electrically connected to contact pads on the second substrate. A conductive plane is formed over a surface of the second substrate.

摘要翻译： 半导体器件具有带有中心区域的第一衬底。 在第一基板的中心区域的周围形成多个凸块。 第一半导体管芯安装到第一衬底的中心区域。 第二半导体管芯在第一衬底的中心区域上安装到第一半导体管芯。 第一和第二管芯的高度小于或等于突起的高度。 第二基板具有导热通道。 与第一管芯相对的第二半导体管芯的表面安装到第二基板的导热通道。 在第二管芯的表面上形成热界面层。 凸块电连接到第二基板上的接触焊盘。 在第二基板的表面上形成导电平面。

公开(公告)号：US20130113093A9

公开(公告)日：2013-05-09

申请号：US13268048

申请日：2011-10-07

申请人： Nazir Ahmad ,  Young-Do Kweon ,  Samuel Tam ,  Kyung-Moon Kim ,  Rajendra D. Pendse

发明人： Nazir Ahmad ,  Young-Do Kweon ,  Samuel Tam ,  Kyung-Moon Kim ,  Rajendra D. Pendse

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points.

摘要翻译： 用于形成金属互连和倒装芯片与衬底的聚合物粘附的方法包括提供具有在其凸起侧上形成的一组凸块的芯片和在其上的金属化层上具有一组互连点的衬底，提供测量量 在突起侧的芯片的中间区域中的聚合物粘合剂，使芯片与衬底对准，使得该组凸块与该组互连点对准，将芯片和衬底朝向彼此挤压，使得一部分 聚合物粘合剂接触基板，并且凸点接触互连点，并且将凸块加热到足够高的温度以在凸块和互连点之间形成冶金连接。

公开(公告)号：US08435834B2

公开(公告)日：2013-05-07

申请号：US12880255

申请日：2010-09-13

申请人： Reza A. Pagaila ,  Rajendra D. Pendse ,  Jun Mo Koo

发明人： Reza A. Pagaila ,  Rajendra D. Pendse ,  Jun Mo Koo

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC分类号： H01L23/28 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/18 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

摘要： A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.

摘要翻译： 半导体管芯具有包括形成在载体上的多条迹线的导电层。 导电层包括与迹线相连接的多个接触垫。 半导体管芯具有形成在接触焊盘上的多个接触焊盘和凸块。 可以在半导体管芯的接触焊盘上形成多个导电柱。 凸块形成在导电柱上。 将半导体管芯安装到导电层上，凸块直接接合到迹线的端部，以提供细间距互连。 密封剂沉积在半导体管芯和导电层上。 导电层包含可湿性材料，以减少封装期间的模具移动。 载体被移除。 在密封剂和半导体管芯上形成互连结构。 可以在导电层上形成绝缘层。

公开(公告)号：US08409920B2

公开(公告)日：2013-04-02

申请号：US12057360

申请日：2008-03-27

申请人： Rajendra D. Pendse ,  Flynn Carson ,  Il Kwon Shim ,  Seng Guan Chow

发明人： Rajendra D. Pendse ,  Flynn Carson ,  Il Kwon Shim ,  Seng Guan Chow

IPC分类号： H01L21/44

CPC分类号： H01L23/49805 ,  H01L21/56 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit package system and method of manufacture therefor includes: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.

摘要翻译： 集成电路封装系统及其制造方法包括：形成区域阵列基板; 在面阵列基板上安装表面导体; 在所述面阵列基板和所述表面导体上形成模制封装体; 在模制包装体中提供一个步骤; 并通过该步骤暴露表面导体。

公开(公告)号：US20120319272A1

公开(公告)日：2012-12-20

申请号：US13596446

申请日：2012-08-28

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/48

CPC分类号： H05K3/3452 ,  H01L21/4846 ,  H01L21/4853 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/11822 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/0989 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/0401

摘要： A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the re-melt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

公开(公告)号：US20120241984A9

公开(公告)日：2012-09-27

申请号：US12959709

申请日：2010-12-03

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L24/17 ,  H01L21/56 ,  H01L21/563 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/528 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/09133 ,  H01L2224/09135 ,  H01L2224/11 ,  H01L2224/1134 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17133 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device has a semiconductor die with a die pad layout. Signal pads in the die pad layout are located primarily near a perimeter of the semiconductor die, and power pads and ground pads are located primarily inboard from the signal pads. The signal pads are arranged in a peripheral row or in a peripheral array generally parallel to an edge of the semiconductor die. Bumps are formed over the signal pads, power pads, and ground pads. The bumps can have a fusible portion and non-fusible portion. Conductive traces with interconnect sites are formed over a substrate. The bumps are wider than the interconnect sites. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate.

摘要翻译： 半导体器件具有具有管芯焊盘布局的半导体管芯。 管芯焊盘布局中的信号焊盘主要位于半导体管芯的周边附近，并且电源焊盘和接地焊盘主要位于信号焊盘的内侧。 信号焊盘被布置在大致平行于半导体管芯的边缘的外围行或周边阵列中。 在信号焊盘，电源焊盘和接地焊盘上形成凸起。 凸块可以具有可熔部分和非易熔部分。 具有互连部位的导电迹线形成在衬底上。 凸块比互连部位宽。 凸块与互连部位接合，使得凸块覆盖互连部位的顶表面和侧表面。 围绕半导体管芯和衬底之间的凸块沉积密封剂。

公开(公告)号：US20120241945A9

公开(公告)日：2012-09-27

申请号：US12947414

申请日：2010-11-16

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/81 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/73 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1134 ,  H01L2224/13017 ,  H01L2224/13019 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81141 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K3/325 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

摘要： A semiconductor device has a semiconductor die with a plurality of bumps or interconnect structures formed over an active surface of the die. The bumps can have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. A plurality of conductive traces with interconnect sites is formed over a substrate. The bumps are wider than the interconnect sites. A masking layer is formed over an area of the substrate away from the interconnect sites. The bumps are bonded to the interconnect sites under pressure or reflow temperature so that the bumps cover a top surface and side surfaces of the interconnect sites. An encapsulant is deposited around the bumps between the die and substrate. The masking layer can form a dam to block the encapsulant from extending beyond the semiconductor die. Asperities can be formed over the interconnect sites or bumps.

摘要翻译： 半导体器件具有形成在管芯的有效表面上的多个凸起或互连结构的半导体管芯。 凸块可以具有可熔部分和不可熔部分，例如形成在导电柱上的导电柱和凸块。 在衬底上形成具有互连部位的多个导电迹线。 凸块比互连部位宽。 在衬底的远离互连位置的区域上形成掩模层。 凸块在压力或回流温度下结合到互连位置，使得凸块覆盖互连位置的顶表面和侧表面。 围绕裸片和衬底之间的凸起沉积密封剂。 掩模层可以形成阻挡以阻止密封剂延伸超过半导体管芯的大坝。 可以在互连部位或凸块上形成凹凸。

公开(公告)号：US20120223428A1

公开(公告)日：2012-09-06

申请号：US13476410

申请日：2012-05-21

申请人： Rajendra D. Pendse

发明人： Rajendra D. Pendse

IPC分类号： H01L23/48 ,  H01L21/50 ,  H01L21/60

CPC分类号： H01L24/16 ,  H01L21/4853 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/1184 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/1312 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48824 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/13099 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A semiconductor device has a semiconductor die and substrate with a plurality of stud bumps formed over the semiconductor die or substrate. The stud bumps include a base portion and stem portion extending from the base portion. The stud bumps include a non-fusible material or fusible material. The semiconductor die is mounted to the substrate with the stud bumps electrically connecting the semiconductor die to the substrate. A width of the base portion is greater than a mating conductive trace formed on the substrate. Alternatively, a vertical interconnect structure, such as a conductive column, is formed over the semiconductor die or substrate. The conductive column can have a tapered sidewall or oval cross sectional area. An underfill material is deposited between the semiconductor die and substrate. The semiconductor die includes a flexible property. The vertical interconnect structure includes a flexible property. The substrate includes a flexible property.

摘要翻译： 半导体器件具有半导体管芯和衬底，其具有形成在半导体管芯或衬底上的多个柱形突起。 柱形凸块包括从基部延伸的基部和杆部。 支柱凸块包括不可熔材料或易熔材料。 半导体管芯安装到基板上，柱形凸块将半导体管芯电连接到基板。 基部的宽度大于形成在基板上的配合导电迹线。 或者，在半导体管芯或衬底上形成诸如导电柱的垂直互连结构。 导电柱可以具有锥形侧壁或椭圆形横截面积。 在半导体管芯和衬底之间沉积底部填充材料。 半导体管芯具有柔性。 垂直互连结构包括灵活的属性。 基板包括柔性。