公开(公告)号：US20160013159A1

公开(公告)日：2016-01-14

申请号：US14755422

申请日：2015-06-30

申请人： Jong-oh KWON

发明人： Jong-oh KWON

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L29/04 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/48 ,  H01L24/05 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/06135 ,  H01L2224/24011 ,  H01L2224/2413 ,  H01L2224/24145 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2224/03

摘要： A chip including a chip body, the chip body including a surface portion and edges surrounding the surface portion, at least one of the edges having a sloped portion, and a side pad on the sloped portion may be provided. A chip-stacked package including a bonding pad on a top surface thereof, a chip on the wiring substrate, the chip including edges and a side pad on the sloped portion, at least one of the edges having a sloped portion, and a conductive line electrically connecting the bonding pad of the wiring substrate to the side pad of the sloped portion may be provided.

摘要翻译： 包括芯片体的芯片，芯片体包括表面部分和围绕表面部分的边缘，可以提供倾斜部分中的至少一个边缘和倾斜部分上的侧部焊盘。 一种芯片堆叠封装，包括在其顶表面上的焊盘，布线基板上的芯片，包括边缘的芯片和倾斜部分上的侧焊盘，至少一个边缘具有倾斜部分，以及导线 可以提供将布线基板的焊盘电连接到倾斜部分的侧焊盘。

公开(公告)号：US20150137366A1

公开(公告)日：2015-05-21

申请号：US14610002

申请日：2015-01-30

申请人： International Business Machines Corporation

发明人： Gregory M. Fritz ,  Eric P. Lewandowski

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/17 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/13006 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13179 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/1713 ,  H01L2224/17163 ,  H01L2224/7525 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81222 ,  H01L2224/81455 ,  H01L2224/81457 ,  H01L2224/8146 ,  H01L2224/81466 ,  H01L2224/818 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/0541 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2224/81121 ,  H01L2924/00012 ,  H01L2224/757 ,  H01L2924/014 ,  H01L2224/05552

摘要： An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process.

摘要翻译： 包括一组反应性材料的焊盘阵列设置在第一衬底上。 通过由时间依赖磁场引起的磁加热，可以选择一组反应性材料。 磁加热可以是涡流加热，滞后加热和/或通过磁弛豫过程加热。 使第二基板上的焊球的阵列与焊盘的阵列接触。 通过施加的磁场在一组磁性材料中引发反应。 在一组反应性材料的反应期间，在形成反应的材料的反应中快速释放热量，熔化焊球并在第一基板和第二基板之间提供粘结。 由于磁加热可以被定位，所以在接合过程中可以最小化衬底的加热和翘曲。

公开(公告)号：US20150115417A1

公开(公告)日：2015-04-30

申请号：US14591014

申请日：2015-01-07

申请人： Infineon Technologies AG

发明人： Reinhard HESS ,  Katharina UMMINGER ,  Gabriel MAIER ,  Markus MENATH ,  Gunther MACKH ,  Hannes EDER ,  Alexander HEINRICH

IPC分类号： H01L23/31 ,  H01L23/485

CPC分类号： H01L23/3171 ,  H01L21/02107 ,  H01L21/30655 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/485 ,  H01L24/05 ,  H01L2224/0236 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/05548 ,  H01L2224/0556 ,  H01L2224/0557 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01046 ,  H01L2924/0103 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

摘要： A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

摘要翻译： 提供了一种制造芯片布置的方法，该方法包括：在载体中形成一个孔，该载体包括至少一个芯片，其中在载体中形成孔包括：选择性地去除载体材料，从而在载体中形成空腔，形成钝化 通过选择性去除载体材料暴露的一个或多个腔壁上的材料; 选择性地去除钝化材料的一部分和通过选择性去除钝化材料暴露的另外的载体材料，其中钝化材料的另一部分保留在至少一个空腔侧壁上; 该方法还包括随后在保留在至少一个空腔侧壁上的钝化材料的另一部分上形成层。

公开(公告)号：US08941212B2

公开(公告)日：2015-01-27

申请号：US13760551

申请日：2013-02-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hsiao-Tsung Yen ,  Cheng-Wei Luo ,  Chin-Wei Kuo ,  Min-Chie Jeng

IPC分类号： H01L21/84 ,  H01L27/08 ,  H01L21/82

CPC分类号： H01L27/08 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0086 ,  H01L21/82 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0566 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/00

摘要： The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

摘要翻译： 本公开涉及提供良好的电感和Q因子的多电平集成电感器。 在一些实施例中，集成电感器具有第一电感结构，其中第一金属层以第一螺旋图案设置在第一IC管芯上，第二电感结构具有以第二螺旋图案设置在第二IC管芯上的​​第二金属层。 第一IC芯片垂直堆叠在第二IC芯片上。 导电互连结构垂直地位于第一和第二IC芯片之间并将第一金属层电连接到第二金属层。 导电互连结构提供在第一和第二电感结构之间相对较大的距离，其提供在大范围频率上具有高Q因子的电感。

公开(公告)号：US20140001634A1

公开(公告)日：2014-01-02

申请号：US13534144

申请日：2012-06-27

申请人： Holger Torwesten ,  Manfred Mengel

发明人： Holger Torwesten ,  Manfred Mengel

IPC分类号： H01L23/52 ,  H01L21/60

CPC分类号： H01L24/83 ,  H01L21/561 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05672 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/2731 ,  H01L2224/27332 ,  H01L2224/27334 ,  H01L2224/29082 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/32245 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83439 ,  H01L2224/83447 ,  H01L2224/83825 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/9202 ,  H01L2224/92143 ,  H01L2224/92147 ,  H01L2224/94 ,  H01L2224/95 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/03 ,  H01L2224/11 ,  H01L21/56 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method for manufacturing a chip package is provided, the method including: forming a layer arrangement over a carrier; arranging a chip including one or more contact pads over the layer arrangement wherein the chip covers at least part of the layer arrangement; and selectively removing one or more portions of the layer arrangement and using the chip as a mask such that at least part of the layer arrangement covered by the chip is not removed.

摘要翻译： 提供了一种用于制造芯片封装的方法，所述方法包括：在载体上形成层布置; 在所述层布置上布置包括一个或多个接触垫的芯片，其中所述芯片覆盖所述层布置的至少一部分; 以及选择性地去除所述层布置的一个或多个部分并使用所述芯片作为掩模，使得所述芯片所​​覆盖的层布置的至少一部分不被去除。

公开(公告)号：US08383505B2

公开(公告)日：2013-02-26

申请号：US13080105

申请日：2011-04-05

申请人： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

发明人： Luc Guerin ,  Mario J. Interrante ,  Michael J. Shapiro ,  Thuy Tran-Quinn ,  Van T. Truong

IPC分类号： H01L21/00

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/03618 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05681 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01026 ,  H01L2224/05552

摘要： A solder ball contact and a method of making a solder ball contact includes: a first insulating layer with a via formed on an integrated circuit (IC) chip and a metal pad; an under bump metallurgy (UBM) structure disposed within the via and on a portion of the first insulating layer, surrounding the via; a second insulating layer formed on an upper surface of an outer portion of the UBM structure that is centered on the via; and a solder ball that fills the via and is disposed above an upper surface of an inner portion of the UBM structure that contacts the via, in which the UBM structure that underlies the solder ball is of a greater diameter than the solder ball.

摘要翻译： 焊球接触和制造焊球接触的方法包括：在集成电路（IC）芯片和金属焊盘上形成有通孔的第一绝缘层; 设置在所述通孔内和所述第一绝缘层的围绕所述通孔的部分上的凸块下冶金（UBM）结构; 第二绝缘层，形成在所述UBM结构的位于所述通孔的中心的外部的上表面上; 以及填充通孔并且设置在UBM结构的与通孔接触的内部的上表面上方的焊球，其中在焊球下面的UBM结构具有比焊球更大的直径。

公开(公告)号：US07825523B2

公开(公告)日：2010-11-02

申请号：US11616852

申请日：2006-12-27

申请人： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

发明人： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/06 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/45099

摘要： A semiconductor package includes a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern, The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region.

摘要翻译： 半导体封装包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体衬底。 在半导体衬底上形成接合焊盘布线图形。 衬垫重排图案电连接到接合焊盘布线图案。衬垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。

公开(公告)号：US07727814B2

公开(公告)日：2010-06-01

申请号：US12218161

申请日：2008-07-10

申请人： Daewoong Suh ,  Amram Eitan ,  Yongki Min

发明人： Daewoong Suh ,  Amram Eitan ,  Yongki Min

IPC分类号： H01L21/00 ,  H01L21/44

CPC分类号： H01L23/49827 ,  B82Y10/00 ,  C09J7/22 ,  C09J9/02 ,  C09J2201/128 ,  C09J2201/602 ,  C09J2203/326 ,  H01L23/49877 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13193 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13666 ,  H01L2224/16145 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/29 ,  H01L2224/29076 ,  H01L2224/29078 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83203 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/026 ,  Y10S977/848 ,  Y10S977/932 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

摘要翻译： 提供互连和互连的方法来连接集成电路的第一部件和第二部件。 互连包括多个碳纳米管（CNT），其在第一部件和第二部件之间提供导电路径。 互连还包括钝化层以填充相邻CNT之间的间隙。 提供制造各向异性导电膜（ACF）和ACF的方法。 ACF包括多个CNT，其在ACF的第一侧和ACF的第二侧之间提供导电路径。 ACF的侧面还可以包括导电的可固化粘合剂层。 在一个实施方案中，导电可固化粘合剂层可以并入B级可交联聚合物和银颗粒。

公开(公告)号：US07576440B2

公开(公告)日：2009-08-18

申请号：US11556156

申请日：2006-11-02

申请人： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

发明人： Young-Hee Song ,  Il-Heung Choi ,  Jeong-Jin Kim ,  Hae-Jeong Sohn ,  Chung-Woo Lee

IPC分类号： H01L23/48 ,  H01L23/34 ,  H01L23/52 ,  H01L23/495 ,  H01L23/525

CPC分类号： H01L24/05 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/49575 ,  H01L23/525 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05116 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05669 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48463 ,  H01L2224/48471 ,  H01L2224/49113 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/10161 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

摘要： A semiconductor chip comprises a semiconductor substrate having integrated circuits formed on a cell region and a peripheral circuit region adjacent to each other. A bond pad-wiring pattern is formed on the semiconductor substrate. A pad-rearrangement pattern is electrically connected to the bond pad-wiring pattern. The pad-rearrangement pattern includes a bond pad disposed over at least a part of the cell region. The bond pad-wiring pattern is formed substantially in a center region of the semiconductor substrate. Thus, with the embodiments of the present invention, the overall chip size can thereby be substantially reduced and an MCP can be fabricated without the problems mentioned above.

摘要翻译： 半导体芯片包括具有形成在单元区域和彼此相邻的外围电路区域的集成电路的半导体基板。 在半导体衬底上形成接合焊盘布线图形。 焊盘重排图案电连接到接合焊盘布线图案。 垫重排图案包括设置在单元区域的至少一部分上的接合焊盘。 接合焊盘布线图形基本上形成在半导体衬底的中心区域中。 因此，利用本发明的实施例，由此可以大大减小总体芯片尺寸，并且可以制造MCP而没有上述问题。

公开(公告)号：US20090068830A1

公开(公告)日：2009-03-12

申请号：US12218161

申请日：2008-07-10

申请人： Daewoong Suh ,  Amran Eitan ,  Yongki Min

发明人： Daewoong Suh ,  Amran Eitan ,  Yongki Min

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  B82Y10/00 ,  C09J7/22 ,  C09J9/02 ,  C09J2201/128 ,  C09J2201/602 ,  C09J2203/326 ,  H01L23/49877 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/05676 ,  H01L2224/0568 ,  H01L2224/11452 ,  H01L2224/1182 ,  H01L2224/1191 ,  H01L2224/13022 ,  H01L2224/13193 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13666 ,  H01L2224/16145 ,  H01L2224/27003 ,  H01L2224/271 ,  H01L2224/29 ,  H01L2224/29076 ,  H01L2224/29078 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83203 ,  H01L2225/06527 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H05K3/323 ,  H05K2201/026 ,  Y10S977/848 ,  Y10S977/932 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01015 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

摘要： A method of interconnecting and an interconnect is provided to connect a first component and a second component of an integrated circuit. The interconnect includes a plurality of Carbon Nanotubes (CNTs), which provide a conducting path between the first component and the second component. The interconnect further includes a passivation layer to fill the gaps between adjacent CNTs. A method of producing Anisotropic Conductive Film (ACF) and an ACF is provided. The ACF includes a plurality of CNTs, which provide a conducting path between a first side of the ACF and a second side of the ACF. The sides of the ACF can also include a conductive curable adhesive layer. In an embodiment, the conductive curable adhesive layer can incorporate a B-stage cross-linkable polymer and silver particles.

摘要翻译： 提供互连和互连的方法来连接集成电路的第一部件和第二部件。 互连包括多个碳纳米管（CNT），其在第一部件和第二部件之间提供导电路径。 互连还包括钝化层以填充相邻CNT之间的间隙。 提供制造各向异性导电膜（ACF）和ACF的方法。 ACF包括多个CNT，其在ACF的第一侧和ACF的第二侧之间提供导电路径。 ACF的侧面还可以包括导电的可固化粘合剂层。 在一个实施方案中，导电可固化粘合剂层可以并入B级可交联聚合物和银颗粒。