公开(公告)号：WO2013038594A1

公开(公告)日：2013-03-21

申请号：PCT/JP2012/005026

申请日：2012-08-08

Applicant: パナソニック株式会社 ,  櫻井 大輔 ,  後川 和也 ,  萩原 清己

Inventor： 櫻井　大輔 ,  後川　和也 ,  萩原　清己

IPC: H01L21/60

CPC classification number: H01L24/10 ,  B23K35/001 ,  B23K35/0222 ,  B23K35/24 ,  B23K35/262 ,  B23K2201/40 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05557 ,  H01L2224/11 ,  H01L2224/1144 ,  H01L2224/11464 ,  H01L2224/1182 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13553 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16501 ,  H01L2224/81075 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81805 ,  H01L2224/81825 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/381 ,  H01L2924/206 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/00012 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/00

Abstract: 　脆弱膜を有する半導体チップ等の電子部品が回路基板等の基板に実装された実装構造において、接続信頼性を高めることができる実装構造を提供する。電子部品（１）の電極端子（４）と基板（２）の電極端子（５）とを接続する接合部が、合金（８）とその合金（８）よりも低弾性率の金属（９）とを含み、かつ、合金（８）が低弾性率の金属（９）で囲まれた断面構造を持つ。

Abstract translation: 提供一种安装结构，其中诸如具有弱膜的半导体芯片的电子部件安装在诸如电路板的基板上，所述安装结构能够增加连接可靠性。 连接电子部件（1）的电极端子（4）和基板（2）的电极端子（5）的接合部包含比合金（8）低的弹性模量的合金（8）和金属（9） ），并且具有其中合金（8）被具有较低弹性模量的金属（9）包围的横截面结构。

公开(公告)号：WO2007076099A2

公开(公告)日：2007-07-05

申请号：PCT/US2006049202

申请日：2006-12-26

Applicant: TESSERA INC ,  HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

Inventor： HABA BELGACEM ,  MOHAMMED ILYAS ,  MITCHELL CRAIG S ,  WARNER MICHAEL ,  THOMPSON JESSE BURL

CPC classification number: H01L21/6835 ,  H01L22/34 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/1601 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A dielectric structure is formed by a molding process, so that a first surface (32, 432) of a dielectric structure is shaped by contact with the mold. The opposite second surface (34, 434) of the dielectric structure is applied onto the front surface of a wafer element (38, 438). The dielectric structure may include protruding bumps (30, 130, 230) and terminals (44, 144, 244) may be formed on the bumps. The bumps may be of a precise height. The terminals lie at a precisely controlled height above the front surface of the wafer element. The terminals may include projecting posts (213, 413) which extend above a surrounding solder mask layer (248, 448) to facilitate engagement with a test fixture. The posts are immersed within solder joints (274) when the structure is bonded to a circuit panel.

Abstract translation: 介电结构通过模制工艺形成，使得介电结构的第一表面（32,432）通过与模具接触而成形。 介电结构的相对的第二表面（34,434）被施加到晶片元件（38,438）的前表面上。 电介质结构可以包括突起凸块（30,130,230），并且端子（44,144,244）可以形成在凸块上。 颠簸可能具有精确的高度。 端子位于晶片元件的前表面上方的精确控制高度处。 端子可以包括在周围的阻焊层（248,448）之上延伸的突出柱（213,413），以便于与测试夹具接合。 当结构粘合到电路板时，柱被浸入焊点（274）内。

公开(公告)号：WO2014071814A1

公开(公告)日：2014-05-15

申请号：PCT/CN2013/086211

申请日：2013-10-30

Applicant: 南通富士通微电子股份有限公司

Inventor： 林仲珉 ,  石磊 ,  沈海军

IPC: H01L23/488

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/78 ,  H01L2224/02166 ,  H01L2224/02331 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/451 ,  H01L2224/78611 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/014

Abstract: 一种芯片封装结构和封装方法，所述封装结构包括：半导体衬底；位于所述半导体衬底内的金属焊盘；位于所述半导体衬底上的绝缘层，所述绝缘层具有暴露所述金属焊盘的开口；位于所述金属焊盘上的球下金属电极；位于所述球下金属电极表面的焊球，所述焊球具有第一围裙结构，所述第一围裙结构覆盖所述球下金属电极底部周围的部分金属焊盘。本发明的芯片封装结构增大了焊球和金属焊盘之间的附着力，提升了芯片封装的可靠性。

公开(公告)号：WO2013141166A1

公开(公告)日：2013-09-26

申请号：PCT/JP2013/057484

申请日：2013-03-15

Applicant: 株式会社NEOMAXマテリアル ,  日立金属株式会社

Inventor： 浅田　賢 ,  西村　絢子

IPC: C25D7/00 ,  B22F1/00 ,  B22F1/02 ,  B23K35/14 ,  B23K35/26 ,  C22C12/00 ,  C22C13/02 ,  C25D17/22 ,  H01L21/60

CPC classification number: B23K35/262 ,  B22F1/025 ,  B23K35/0244 ,  B23K35/264 ,  C22C12/00 ,  C22C13/02 ,  C25D7/00 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/11334 ,  H01L2224/13147 ,  H01L2224/1316 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13655 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/3651 ,  H05K3/3478 ,  H05K2203/041 ,  H01L2924/01083 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: 　本発明による実施形態のはんだ被覆ボール（１０Ａ）は、ボール状のコア（１１）と、コア（１１）を被覆するように形成されたはんだ層（１２）とを有し、はんだ層（１２）は、ＳｎとＢｉとを含み、Ｂｉ含有率が４５質量％以上６５質量％以下で、且つ、Ｂｉの含有率は、内側で高く、外側で低い。他のはんだ被覆ボール（１０Ｂ）は、コア１１とはんだ層１２との間にＮｉめっき層１３をさらに有する。

Abstract translation: 根据本发明的一个实施方案的焊料涂覆的球（10A）具有形成为涂覆芯（11）的球形芯（11）和焊料层（12），焊料层（12）包括 Sn和Bi，Bi含量为45质量％〜65质量％，Bi含量高，外部为低。 另一个焊料涂覆球（10B）还在芯部（11）和焊料层（12）之间具有Ni镀层（13）。

公开(公告)号：WO2012167027A2

公开(公告)日：2012-12-06

申请号：PCT/US2012/040388

申请日：2012-06-01

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED ,  WEST, Jeffrey, Alan

Inventor： WEST, Jeffrey, Alan

IPC: H01L21/768 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L23/538 ,  H01L21/563 ,  H01L23/481 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2224/13681 ,  H01L2224/14181 ,  H01L2224/1613 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01074

Abstract: A method (100) of protecting through-substrate via (TSV) die from bonding damage includes providing a substrate including a plurality of TSV die having a topside including active circuitry, a bottomside, and a plurality of TSVs that include an inner metal core that reaches from the topside to protruding TSV tips that extend out from the bottomside (101). A protective layer is formed on or applied to the bottomside of the TSV die including between and over the protruding TSV tips (102). The TSV die is bonded with its topside down onto a workpiece having a workpiece surface and its bottomside up and in contact with a bond head (104). The protective layer reduces damage from the bonding process including warpage of the TSV die by preventing the bond head from making direct contact to the protruding TSV tips.

Abstract translation: 保护通过（TSV）管芯的通过衬底的接合损伤的方法（100）包括提供包括多个TSV管芯的衬底，所述TSV管芯具有包括有源电路，底部和多个TSV的顶部，所述TSV包括内部金属芯， 从顶部到达突出的TSV尖端，从底部延伸出来（101）。 在TSV管芯的底部上形成保护层，包括在突出的TSV尖端（102）之间和之上。 TSV模具的上下结合到具有工件表面的工件上，并且其底部向上并与接合头（104）接触。 保护层通过防止接合头与突出的TSV尖端直接接触来减少接合过程中的损伤，包括TSV模头的翘曲。

公开(公告)号：WO02007208A1

公开(公告)日：2002-01-24

申请号：PCT/FR2000/002063

申请日：2000-07-18

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01R43/02 ,  H05K3/34

CPC classification number: H05K3/3484 ,  H01L21/4853 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/05573 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1316 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01R43/0249 ,  H01R43/0256 ,  H05K3/3426 ,  H05K2201/10704 ,  H05K2201/10984 ,  H05K2203/0113 ,  H05K2203/0338 ,  Y02P70/613 ,  H01L2924/01028 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: The invention concerns a method for making an integrated circuit (40) capable of being surface-mounted which consists in first making a housing with a rear face and an array of connection pins extending underneath said rear surface perpendicular thereto, and then in forming at the end of each pin a ball (44) of alloy with low melting point enclosing said end and welded thereto. The invention also concerns an integrated circuit (40) capable of being surface-mounted, comprising a housing with a rear surface and an array of connection pins, with substantially constant cross-section along the pin, extending underneath said rear surface perpendicular thereto. A ball (44) of alloy with low melting point is welded to the end of each pin (42) enclosing said end. The invention is applicable to surface-mounted integrated circuits.

Abstract translation: 本发明涉及一种用于制造能够被表面安装的集成电路（40）的方法，其包括首先制造具有后表面的壳体和在所述后表面垂直于其的下方延伸的连接销阵列，然后在 每个销的端部具有围绕所述端部并焊接到其上的低熔点合金球（44）。 本发明还涉及一种能够被表面安装的集成电路（40），其包括具有后表面和连接销阵列的壳体，沿着销具有基本上恒定的横截面，在垂直于其的所述后表面的下方延伸。 将具有低熔点的合金球（44）焊接到封闭所述端部的每个销（42）的端部。 本发明适用于表面安装集成电路。

公开(公告)号：WO1991020095A1

公开(公告)日：1991-12-26

申请号：PCT/US1990005931

申请日：1990-10-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  AGARWALA, Birendra, Nath ,  AHSAN, Aziz, Mohammed ,  BROSS, Arthur ,  CHADURJIAN, Mark, Frank ,  KOOPMAN, Nicholas, George ,  LEE, Li-Chung ,  PUTTLITZ, Karl, J. ,  RAY, Sudipta, Kumar ,  RYAN, James, Gardner ,  SCHAEFER, Joseph, George ,  SRIVASTAVA, Kamalesh, Kumar ,  TOTTA, Paul, Anthony ,  WALTON, Erick, Gregory ,  WIRSING, Adolf, Ernest

IPC: H01L23/485

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13669 ,  H01L2224/1367 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/13676 ,  H01L2224/13679 ,  H01L2224/1368 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/3431 ,  H05K3/3457 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

Abstract: The present invention relates generally to a new interconnection and a method for making the same, and more particularly, to an elongated solder interconnection and a method for making the same. On an electronic carrier, a pad is formed on which a solder mass is deposited and capped with a metal layer, thereby forming an elongated solder interconnection. A further elongated solder interconnection can now be formed by forming a second solder mass on the first solder mass that has been capped by a metal layer. Additional elongated solder interconnection can be formed by capping the preceding solder mass and/or the last solder mass with a metal capping layer. Alternatively, the encapsulating layer can be in the form of a sidewall spacer formed on the sidewalls of the solder mass.

公开(公告)号：WO2014207590A3

公开(公告)日：2015-05-07

申请号：PCT/IB2014061968

申请日：2014-06-05

Applicant: KONINKL PHILIPS NV

Inventor： LEI JIPU ,  SCHIAFFINO STEFANO ,  NICKEL ALEXANDER H ,  NG MOOI GUAN ,  AKRAM SALMAN

IPC: H01L21/60 ,  H01L21/48 ,  H01L23/485 ,  H01L23/498

CPC classification number: H01L24/11 ,  B23K1/20 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0345 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11825 ,  H01L2224/11826 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/119 ,  H01L2224/11902 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14104 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12041 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/1146 ,  H01L2924/00

Abstract: A technique is disclosed for causing the top surfaces of solder bumps on a chip (40) to be in the same plane to ensure a more reliable bond between the chip (40) and a substrate (62). The chip (40) is provided with solder pads (42, 44) that may have different heights. A dielectric layer (50) is formed between the solder pads (42, 44). A relatively thick metal layer (52) is plated over the solder pads (42, 44). The metal layer (52) is planarized to cause the top surfaces of the metal layer (52) portions over the solder pads (42, 44) to be in the same plane and above the dielectric layer (50). A substantially uniform thin layer of solder (58) is deposited over the planarized metal layer portions (52) so that the top surfaces of the solder bumps are substantially in the same plane, which may be substantially parallel to the top surface of the chip (40) or at an angle relative to the top surface of the chip (40). The chip (40) is then positioned over a substrate (62) having corresponding metal pads (64), and the solder (58) is reflowed or ultrasonically bonded to the substrate pads (64).

Abstract translation: 公开了一种技术，用于使芯片（40）上的焊料凸起的顶表面位于同一平面中，以确保芯片（40）和衬底（62）之间的更可靠的结合。 芯片（40）设置有可能具有不同高度的焊盘（42,44）。 在焊盘（42,44）之间形成介电层（50）。 相对厚的金属层（52）被电镀在焊盘（42,44）上。 金属层（52）被平坦化，使得焊料焊盘（42,44）之上的金属层（52）的顶部表面位于同一平面内并在电介质层（50）的上方。 在平坦化的金属层部分（52）上沉积基本上均匀的薄层的焊料（58），使得焊料凸块的顶表面基本上处于与芯片的顶表面基本平行的同一平面（ 40）或相对于芯片（40）的顶表面成一定角度。 然后将芯片（40）定位在具有对应的金属焊盘（64）的衬底（62）上方，并且焊料（58）被回流或超声波结合到衬底焊盘（64）。

公开(公告)号：WO2014209404A1

公开(公告)日：2014-12-31

申请号：PCT/US2013/048792

申请日：2013-06-29

Applicant: INTEL CORPORATION

Inventor： LEE, Kevin J. ,  JEONG, James Y. ,  CHANG, Hsiao-Kang ,  MUIRHEAD, John ,  TELANG, Adwait ,  PURI, Puneesh ,  KANG, Jiho ,  PATEL, Nitin M.

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/48

CPC classification number: H01L23/5384 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76871 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03424 ,  H01L2224/03464 ,  H01L2224/03823 ,  H01L2224/03825 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05548 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/11002 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/116 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13664 ,  H01L2224/16145 ,  H01L2924/13091 ,  H01L2924/381 ,  H01L2924/00 ,  H01L2924/01022 ,  H01L2924/01073 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/01029 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014

Abstract: A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a "plate through resist" type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

Abstract translation: 描述了三维互连结构和制造方法，其中金属再分布层（RDL）与硅通孔（TSV）集成并且使用“平板通过抗蚀剂”型工艺流程。 氮化硅或碳化硅钝化层可以设置在薄化的器件晶片背面和RDL之间，以在工艺流程期间提供密封屏障和抛光停止层。

公开(公告)号：WO2014044435A1

公开(公告)日：2014-03-27

申请号：PCT/EP2013/065296

申请日：2013-07-19

Applicant: ATOTECH DEUTSCHLAND GMBH

Inventor： BECK, Thomas ,  STEINBERGER, Gerhard ,  WALTER, Andreas

IPC: H01L21/60 ,  H01L23/485

CPC classification number: H01L24/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/10145 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11821 ,  H01L2224/11822 ,  H01L2224/11823 ,  H01L2224/11825 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13664 ,  H01L2224/13669 ,  H01L2224/13673 ,  H01L2224/13676 ,  H01L2224/16507 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3841 ,  H01L2924/01074 ,  H01L2924/01015 ,  H01L2924/01005 ,  H01L2924/01042 ,  H01L2924/20751 ,  H01L2924/2076 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2224/05552

Abstract: The present invention relates to a method for forming a copper pillar on a semi-conducting substrate, the copper pillar having an underbump metallization area comprising a metal less noble than copper and optionally a solder bump on the top portion, and having a layer of a second metal selected from tin, tin alloys, silver, and silver alloys deposited onto the side walls of said copper pillar. A layer of a first metal which is more noble than copper is deposited onto the entire outer surface of the copper pillar prior to deposition of the second metal layer. The layer of a second metal then has at least a reduced number of undesired pin-holes and serves as a protection layer for the underlying copper pillar.

Abstract translation: 本发明涉及一种在半导体基板上形成铜柱的方法，所述铜柱具有底部金属化区域，该底部金属化区域包括比铜更贵的金属，并且可选地在顶部上具有焊料凸块，并且具有 选自沉积在所述铜柱的侧壁上的锡，锡合金，银和银合金的第二金属。 在沉积第二金属层之前，在铜柱的整个外表面上沉积比铜更贵的第一金属层。 然后，第二金属层至少具有减少数量的不期望的针孔，并且用作下面的铜柱的保护层。