Patent search aee:"STATS ChipPAC Pte. Ltd." Page 10

91.

发明授权
Integrated circuit packaging system with photoimagable dielectric-defined trace and method of manufacture thereof 有权

公开(公告)号：US09679769B1

公开(公告)日：2017-06-13

申请号：US15199751

申请日：2016-06-30

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Zigmund Ramirez Camacho , Bartholomew Liao Chung Foh , Sheila Marie L. Alvarez , Dao Nguyen Phu Cuong , HeeJo Chi

IPC: H01L21/48 , H01L21/56 , H01L23/00 , H01L23/12 , H01L23/485 , H01L21/033 , H01L23/522 , H01L21/768 , H01L23/528 , H01L23/532

CPC classification number: H01L21/0335 , H01L21/485 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L21/568 , H01L21/76879 , H01L23/3128 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L23/49894 , H01L23/5226 , H01L23/528 , H01L23/53233 , H01L23/53242 , H01L24/03 , H01L24/08 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/43 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/05026 , H01L2224/131 , H01L2224/16237 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/81447 , H01L2224/81815 , H01L2224/83005 , H01L2224/85005 , H01L2224/85447 , H01L2924/00014 , H01L2924/14 , H01L2924/1461 , H01L2924/15311 , H01L2924/181 , H01L2924/3511 , H01L2924/37001 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00

Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a photoimagable dielectric layer having a trace opening for exposing the carrier; a trace within the trace opening; an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having a bond pad opening for exposing the trace; an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through the bond pad opening; an encapsulation directly on the integrated circuit and the inner solder resist layer; and an external interconnect electrically coupled to the trace and the integrated circuit.

92.

发明申请
Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation 审中-公开

公开(公告)号：US20170098612A1

公开(公告)日：2017-04-06

申请号：US15381281

申请日：2016-12-16

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin , Kang Chen , Jianmin Fang , Xia Feng

IPC: H01L23/538 , H01L21/768 , H01L23/31 , H01L21/56

CPC classification number: H01L23/5389 , H01L21/31051 , H01L21/56 , H01L21/568 , H01L21/768 , H01L21/76802 , H01L21/78 , H01L23/3107 , H01L23/49816 , H01L24/19 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/94 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00 , H01L2224/03

Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.

93.

发明申请
Semiconductor Device and Method of Using Substrate Having Base and Conductive Posts to Form Vertical Interconnect Structure in Embedded Die Package 审中-公开

公开(公告)号：US20170098610A1

公开(公告)日：2017-04-06

申请号：US15380788

申请日：2016-12-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim , Jun Mo Koo , Pandi C. Marimuthu , Yaojian Lin , See Chian Lim

IPC: H01L23/538 , H01L23/00 , H01L23/31

CPC classification number: H01L23/5384 , H01L21/486 , H01L21/568 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/5386 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/9222 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2924/00 , H01L2924/01082 , H01L2224/03 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

94.

发明授权
Semiconductor device and method for forming openings and trenches in insulating layer by first LDA and second LDA for RDL formation 有权

公开(公告)号：US09607958B2

公开(公告)日：2017-03-28

申请号：US14512614

申请日：2014-10-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin , Pandi C. Marimuthu , Kang Chen

IPC: H01L23/00 , H01L23/31 , H01L23/29 , H01L21/56 , H01L23/538 , H01L23/498

CPC classification number: H01L24/14 , H01L21/561 , H01L21/565 , H01L21/568 , H01L23/291 , H01L23/3121 , H01L23/3135 , H01L23/49816 , H01L23/5389 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L2224/02351 , H01L2224/0236 , H01L2224/02372 , H01L2224/02379 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0348 , H01L2224/0361 , H01L2224/0391 , H01L2224/0401 , H01L2224/04105 , H01L2224/05548 , H01L2224/05552 , H01L2224/05557 , H01L2224/05567 , H01L2224/06181 , H01L2224/11334 , H01L2224/1146 , H01L2224/11849 , H01L2224/12105 , H01L2224/13008 , H01L2224/13022 , H01L2224/13023 , H01L2224/13024 , H01L2224/13111 , H01L2224/13113 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/94 , H01L2924/00013 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/20101 , H01L2924/00 , H01L2224/13099 , H01L2224/05099 , H01L2224/05599 , H01L2924/00014 , H01L2224/03 , H01L2224/11 , H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.

95.

发明授权
Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die 有权
Title translation: 半导体器件以及从基底衬底形成基底引线作为用于堆叠半导体管芯的间隙的方法

公开(公告)号：US09589910B2

公开(公告)日：2017-03-07

申请号：US13846014

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila , Dioscoro A. Merilo

IPC: H01L23/488 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/495 , H01L25/065 , H01L25/00 , H01L23/538 , H01L25/10

CPC classification number: H01L23/562 , H01L21/4832 , H01L21/56 , H01L21/561 , H01L23/495 , H01L23/49575 , H01L23/49582 , H01L23/5384 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/06181 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/48091 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/18161 , H01L2224/81 , H01L2224/05552 , H01L2924/00 , H01L2924/00012

Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die.

Abstract translation: 半导体器件具有带有第一和第二相对表面的基底基板。在基底基板的第一表面上形成第一耐蚀刻导电层。第二耐蚀刻导电层形成在基底衬底的第二表面上。第一半导体管芯具有形成在第一管芯的有效表面上的接触焊盘上的凸起。第一管芯安装在第一导电层的第一表面上。密封剂沉积在第一管芯和基底衬底上。去除基底衬底的一部分以在第一和第二导电层的相对部分之间形成电隔离的底部引线。第二半导体管芯安装在密封剂上方，第一导电层的第二表面位于基底引线之间。基部引线的高度大于第二管芯的厚度。

96.

发明授权
Semiconductor device and method of forming a fan-in package-on-package structure using through silicon vias 有权
Title translation: 半导体器件和通过硅通孔形成扇入式封装封装结构的方法

公开(公告)号：US09559046B2

公开(公告)日：2017-01-31

申请号：US12209838

申请日：2008-09-12

Applicant: Hyunil Bae , Youngchul Kim , Myungkil Lee

Inventor： Hyunil Bae , Youngchul Kim , Myungkil Lee

IPC: H01L21/00 , H01L23/498 , H01L21/56 , H01L23/48 , H01L25/065 , H01L25/10 , H01L25/00 , H01L25/03 , H01L23/31 , H01L23/525 , H01L23/00

CPC classification number: H01L23/49816 , H01L21/563 , H01L23/3128 , H01L23/481 , H01L23/525 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/13025 , H01L2224/13099 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06541 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/12041 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15174 , H01L2924/15184 , H01L2924/15311 , H01L2924/1532 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A semiconductor device is made by providing a first semiconductor die having a plurality of contact pads formed over a first surface of the first semiconductor die and having a plurality of through-silicon vias (TSVs) formed within the first semiconductor die. A second semiconductor die is mounted to the first surface of the first semiconductor die using a plurality of solder bumps. At least one of the solder bumps is in electrical communication with the TSVs in the first semiconductor die. The second semiconductor die is mounted to a printed circuit board (PCB) using an adhesive material. A plurality of solder bumps is formed to connect the contact pads of the first semiconductor die to the PCB. An encapsulant is deposited over the first semiconductor die and the second semiconductor die. An interconnect structure is formed over a back surface of the PCB.

Abstract translation: 通过提供具有形成在第一半导体管芯的第一表面上的多个接触焊盘并且具有形成在第一半导体管芯内的多个穿硅通孔（TSV）来制造半导体器件。使用多个焊料凸块将第二半导体管芯安装到第一半导体管芯的第一表面。至少一个焊料凸块与第一半导体管芯中的TSV电连通。第二半导体管芯使用粘合剂材料安装到印刷电路板（PCB）上。形成多个焊料凸块以将第一半导体管芯的接触焊盘连接到PCB。密封剂沉积在第一半导体管芯和第二半导体管芯上。互连结构形成在PCB的背面上。

97.

发明授权
Semiconductor device and method of using substrate having base and conductive posts to form vertical interconnect structure in embedded die package 有权
Title translation: 使用具有基极和导电柱的衬底的半导体器件和方法在嵌入式芯片封装中形成垂直互连结构

公开(公告)号：US09559039B2

公开(公告)日：2017-01-31

申请号：US13800807

申请日：2013-03-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim , Jun Mo Koo , Pandi C. Marimuthu , Yaojian Lin , See Chian Lim

IPC: H01L23/48 , H01L21/48 , H01L23/498 , H01L23/538 , H01L23/00 , H01L25/10 , H01L25/00 , H01L21/56 , H01L23/31

CPC classification number: H01L23/5384 , H01L21/486 , H01L21/568 , H01L23/3128 , H01L23/3171 , H01L23/3192 , H01L23/481 , H01L23/49816 , H01L23/5386 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/96 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/11849 , H01L2224/11901 , H01L2224/12105 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/9222 , H01L2224/94 , H01L2224/97 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/1035 , H01L2225/1052 , H01L2225/1058 , H01L2924/00014 , H01L2924/01322 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/00012 , H01L2924/00 , H01L2924/01082 , H01L2224/03 , H01L2224/45099 , H01L2224/45015 , H01L2924/207

Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.

Abstract translation: 半导体器件具有包括基底和从基底延伸的多个导电柱的基底。衬底可以是晶片形状，面板或单体形式。导电柱可以具有圆形，矩形，锥形或变窄的中间形状。通过导电柱之间的底座中的开口设置半导体管芯。半导体管芯延伸到导电柱之上，或者设置在导电柱的下方。密封剂沉积在半导体管芯上并且在导电柱周围。去除基底和一部分密封剂以电绝缘导电柱。在半导体管芯，密封剂和导电柱上形成互连结构。在半导体管芯，密封剂和导电柱上形成绝缘层。半导体封装设置在半导体管芯上并电连接到导电柱。

98.

发明授权
Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield 有权
Title translation: 在衬底中形成孔以互连顶部屏蔽和接地屏蔽的半导体器件和方法

公开(公告)号：US09543258B2

公开(公告)日：2017-01-10

申请号：US15011311

申请日：2016-01-29

Applicant: STATS ChipPAC, Ltd.

Inventor： OhHan Kim , SunMi Kim , KyungHoon Lee

IPC: H01L23/60 , H01L21/56 , H01L23/29 , H01L23/31 , H01L23/552 , H01L23/00

CPC classification number: H01L23/60 , H01L21/561 , H01L21/563 , H01L23/29 , H01L23/3121 , H01L23/3135 , H01L23/552 , H01L24/97 , H01L2224/05026 , H01L2224/05573 , H01L2224/16225 , H01L2224/97 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01047 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2924/00 , H01L2224/05599

Abstract: A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die.

Abstract translation: 半导体器件包括多层衬底。接地屏蔽层设置在基板的层之间并且电连接到接地点。多个半导体管芯通过接地屏蔽件安装到衬底上。接地护罩延伸超过多个半导体管芯的覆盖区。在多个半导体管芯和衬底上形成密封剂。切割通道形成在密封剂中，在多个半导体管芯之间，并在接地屏蔽层之上。沿着切割通道形成多个金属填充的孔，并延伸到基板中并通过接地屏蔽。在多个半导体管芯上形成顶部屏蔽，并通过金属填充的孔电连接和机械地连接到接地屏蔽层。顶部和接地屏蔽被配置为阻止相对于设置在半导体管芯中的集成无源器件产生的电磁干扰。

99.

发明授权
Semiconductor device and method of forming no-flow underfill material around vertical interconnect structure 有权
Title translation: 围绕垂直互连结构形成无流动底部填充材料的半导体器件和方法

公开(公告)号：US09524955B2

公开(公告)日：2016-12-20

申请号：US13423782

申请日：2012-03-19

Applicant: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow

Inventor： Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow

IPC: H01L23/02 , H01L25/10 , H01L21/56 , H01L23/31 , H01L25/065 , H01L25/03 , H01L23/00

CPC classification number: H01L25/105 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/32 , H01L24/81 , H01L24/96 , H01L24/97 , H01L25/03 , H01L25/0657 , H01L2224/0401 , H01L2224/1134 , H01L2224/12105 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/73265 , H01L2224/81203 , H01L2224/81205 , H01L2224/81801 , H01L2224/92 , H01L2224/96 , H01L2225/06517 , H01L2225/06541 , H01L2225/06582 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0103 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/09701 , H01L2924/12041 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2224/82 , H01L2924/00 , H01L2924/00014 , H01L2224/11 , H01L2224/03

Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.

Abstract translation: 通过在第一牺牲载体上形成导电层制成半导体器件。在导电层上形成焊料凸块。在第一载体，导电层和焊料凸块上沉积无流动的底部填充材料。将半导体管芯或部件压缩成无流动底部填充材料以与导电层电接触。无流动底部填充材料和第一焊料凸块的表面被平坦化。第一互连结构形成在无流动底部填充材料的第一表面上。第一互连结构电连接到焊料凸块。第二牺牲载体安装在第一互连结构上。第二互连结构形成在无流动底部填充材料的第二侧上。第二互连结构电连接到第一焊料凸块。半导体器件可以通过焊料凸块堆叠和电连接。