公开(公告)号：US20140319522A1

公开(公告)日：2014-10-30

申请号：US13870026

申请日：2013-04-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Karen P. McLaughlin ,  Ekta Misra ,  Christopher D. Muzzy ,  Eric D. Perfecto ,  Wolfgang Sauter

IPC分类号： H01L23/00

CPC分类号： H01L24/11 ,  H01L22/34 ,  H01L23/3192 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/11914 ,  H01L2224/13023 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13147 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2224/05552

摘要： Disclosed are a method for metallization during semiconductor wafer processing and the resulting structures. In this method, a passivation layer is patterned with first openings aligned above and extending vertically to metal structures below. A mask layer is formed and patterned with second openings aligned above the first openings, thereby forming two-tier openings extending vertically through the mask layer and passivation layer to the metal structures below. An electrodeposition process forms, in the two-tier openings, both under-bump pad(s) and additional metal feature(s), which are different from the under-bump pad(s) (e.g., a wirebond pad; a final vertical section of a crackstop structure; and/or a probe pad). Each under-bump pad and additional metal feature initially comprises copper with metal cap layers thereon. The mask layer is removed, an additional mask layer is formed and patterned with third opening(s) exposing only the under-bump pad(s) and solder material is deposited on the under-bump pad(s).

摘要翻译： 公开了半导体晶片处理期间的金属化方法和所得到的结构。 在该方法中，钝化层被图案化，其中第一开口在上方对齐并垂直延伸到下面的金属结构。 形成掩模层并用第一开口对准的第二开口进行图案化，从而形成垂直延伸穿过掩模层和钝化层到下面的金属结构的两层开口。 电沉积工艺在双层开口中形成凸点下焊盘和附加的金属部件，其不同于凸块下焊盘（例如，引线焊盘;最终垂直的） 裂缝结构部分和/或探针垫）。 每个凸点下焊盘和附加的金属特征最初包括铜上的金属盖层。 除去掩模层，形成另外的掩模层并用仅暴露凸块下焊盘的第三开口图案化，并且将焊料材料沉积在凸块下焊盘上。

公开(公告)号：US20140284819A1

公开(公告)日：2014-09-25

申请号：US14295791

申请日：2014-06-04

申请人： Infineon Technologies Austria AG

发明人： Rudolf Zelsacher ,  Paul Ganitzer

IPC分类号： H01L23/00 ,  H01L23/498

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L21/6835 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3736 ,  H01L23/492 ,  H01L23/49575 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05214 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/3223 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4823 ,  H01L2224/73265 ,  H01L2224/8382 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  Y02P80/30 ,  H01L2224/45099 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method for manufacturing semiconductor devices is disclosed. In one embodiment a semiconductor substrate having a first surface, a second surface opposite to the first surface and a plurality of semiconductor components is provided. The semiconductor substrate has a device thickness. At least one metallisation layer is formed on the second surface of the semiconductor substrate. The metallisation layer has a thickness which is greater than the device thickness.

摘要翻译： 公开了半导体器件的制造方法。 在一个实施例中，提供具有第一表面，与第一表面相对的第二表面和多个半导体部件的半导体衬底。 半导体衬底具有器件厚度。 在半导体衬底的第二表面上形成至少一个金属化层。 金属化层的厚度大于器件厚度。

公开(公告)号：US20140070410A1

公开(公告)日：2014-03-13

申请号：US14084745

申请日：2013-11-20

申请人： STATS ChipPAC, Ltd.

发明人： DaeSik Choi ,  JoonYoung Choi ,  WonIl Kwon

IPC分类号： H01L23/498

CPC分类号： H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02123 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05186 ,  H01L2224/0519 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00

摘要： A semiconductor wafer has a contact pad. A first insulating layer is formed over the wafer. A second insulating layer is formed over the first insulating layer and contact pad. A portion of the second insulating layer is removed to expose the contact pad. A first UBM layer is formed over and follows a contour of the second insulating layer and contact pad to create a well over the contact pad. A first buffer layer is formed in the well over the first UBM layer and the contact pad. A second UBM layer is formed over the first UBM layer and first buffer layer. A third UBM layer is formed over the second UBM layer. A bump is formed over the third UBM layer. The first buffer layer reduces stress on the bump and contact pad. A second buffer layer can be formed between the second and third UBM layers.

摘要翻译： 半导体晶片具有接触垫。 在晶片上形成第一绝缘层。 在第一绝缘层和接触垫上形成第二绝缘层。 去除第二绝缘层的一部分以露出接触垫。 第一UBM层形成在第二绝缘层和接触垫的轮廓之上并且跟随第二绝缘层和接触垫的轮廓以在接触垫上产生良好的孔。 在第一UBM层和接触垫上的阱中形成第一缓冲层。 在第一UBM层和第一缓冲层上形成第二UBM层。 在第二UBM层上形成第三UBM层。 在第三UBM层上形成凸块。 第一个缓冲层减少了凸块和接触垫上的应力。 可以在第二和第三UBM层之间形成第二缓冲层。

公开(公告)号：US20130260556A1

公开(公告)日：2013-10-03

申请号：US13431343

申请日：2012-03-27

申请人： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

发明人： Mukta G. Farooq ,  John A. Fitzsimmons ,  Troy L. Graves-Abe

IPC分类号： H01L21/288 ,  H01L21/683

CPC分类号： H01L21/76898 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76879 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68359 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/11 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/94 ,  Y10T29/41 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/014

摘要： According to one embodiment of the present invention, a method of plating a TSV hole in a substrate is provided. The TSV hole may include an open end terminating at a conductive pad, a stack of wiring levels, and a plurality of chip interconnects. The method of plating a TSV may include attaching a handler to the plurality of chip interconnects, the handler having a conductive layer in electrical contact with the plurality of chip interconnects; exposing a closed end of the TSV hole, including the conductive pad, to an electrolyte solution; and applying an electrical potential along an electrical path from the conductive layer to the conductive pad causing conductive material from the electrolyte solution to deposit on the conductive pad and within the TSV hole, the electrical path including the conductive layer, the plurality of chip interconnects, the stack of wiring levels and the conductive pad.

公开(公告)号：US20130062766A1

公开(公告)日：2013-03-14

申请号：US13674611

申请日：2012-11-12

申请人： Taiwan Semiconductor Manufacturing Company

发明人： Kai-Ming Ching

IPC分类号： H01L23/498

CPC分类号： H01L24/05 ,  H01L23/5283 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02126 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/16059 ,  H01L2224/16147 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8114 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2224/05552

摘要： A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.

公开(公告)号：US20130049190A1

公开(公告)日：2013-02-28

申请号：US13221517

申请日：2011-08-30

申请人： Roden R. Topacio ,  Neil McLellan

发明人： Roden R. Topacio ,  Neil McLellan

IPC分类号： H01L23/488 ,  H01L21/58 ,  H01L21/283

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/115 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/06 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/00 ,  H01L2224/05552

摘要： Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes depositing a layer of a first metallic material on a semiconductor chip. The first layer has a first physical quantity. A layer of a second metallic material is deposited on the layer of the first metallic material. The second layer has a second physical quantity. The first and second layers are reflowed to form a solder structure with a desired ratio of the first metallic material to the second metallic material.

公开(公告)号：US20120261812A1

公开(公告)日：2012-10-18

申请号：US13086672

申请日：2011-04-14

申请人： Roden R. Topacio

发明人： Roden R. Topacio

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/03902 ,  H01L2224/03916 ,  H01L2224/0401 ,  H01L2224/05007 ,  H01L2224/05019 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05562 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05655 ,  H01L2224/10126 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00 ,  H01L2224/81805

摘要： Various semiconductor chip solder bump and underbump metallization (UBM) structures and methods of making the same are disclosed. In one aspect, a method is provided that includes providing a semiconductor chip that has a conductor pad and a passivation structure over the conductor pad. A first metallic layer is applied on the passivation structure and in electrical contact with the conductor pad. The first metallic layer covers a first portion but not a second portion of the passivation structure. A second metallic layer is applied to the first metallic layer. A polymer layer is applied to the second metallic layer. The polymer layer includes a first opening in alignment with the first metallic layer that exposes a portion of the second layer. A conducting solder barrier layer is applied to the exposed portion of the second metallic layer.

摘要翻译： 公开了各种半导体芯片焊料凸块和底部金属化（UBM）结构及其制造方法。 在一个方面，提供了一种方法，其包括提供在导体焊盘上具有导体焊盘和钝化结构的半导体芯片。 第一金属层施加在钝化结构上并与导体焊盘电接触。 第一金属层覆盖钝化结构的第一部分而不是第二部分。 将第二金属层施加到第一金属层。 将聚合物层施加到第二金属层。 聚合物层包括与暴露第二层的一部分的第一金属层对准的第一开口。 导电焊料阻挡层被施加到第二金属层的暴露部分。

公开(公告)号：US20120074572A1

公开(公告)日：2012-03-29

申请号：US12891865

申请日：2010-09-28

申请人： Thomas FISCHER ,  Juergen FOERSTER ,  Werner ROBL ,  Andreas STUECKJUERGEN

发明人： Thomas FISCHER ,  Juergen FOERSTER ,  Werner ROBL ,  Andreas STUECKJUERGEN

IPC分类号： H01L23/532 ,  H01L21/306 ,  H01L21/768

CPC分类号： H01L23/535 ,  H01L21/30604 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L2221/1078 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05193 ,  H01L2224/05647 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

摘要翻译： 一个或多个实施例涉及制造半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成分离层; 在分离层上形成导电层; 并湿式蚀刻导电层。

公开(公告)号：US08115306B2

公开(公告)日：2012-02-14

申请号：US12705277

申请日：2010-02-12

申请人： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

发明人： Chia Yong Poo ,  Boon Suan Jeung ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Lou ,  Eng Meow Koon ,  Ser Bok Leng ,  Chun Swee Kwang ,  So Chee Chung ,  Ho Kwok Song

IPC分类号： H01L23/48

CPC分类号： H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/93 ,  H01L27/105 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/08237 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80898 ,  H01L2224/93 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00

摘要： An apparatus comprises an integrated circuit die including a main body having a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer. The integrated circuit die also includes a bond pad on the main body, an edge contact at the peripheral edge surface and a line connecting the bond pad to the edge contact. The edge contact includes a bottom surface that substantially in the same plane as a surface of an encapsulant encasing the die. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 一种装置包括集成电路管芯，其包括具有顶层，底层和在顶层和底层之间延伸的周边边缘表面的主体。 集成电路管芯还包括主体上的接合焊盘，外围边缘表面处的边缘接触以及将接合焊盘连接到边缘接触件的线。 边缘接触包括底面，其基本上在与包封模具的密封剂的表面相同的平面内。 公开了附加装置，系统和方法。

公开(公告)号：US20110269311A1

公开(公告)日：2011-11-03

申请号：US13097026

申请日：2011-04-28

申请人： Bruce C. Fleischhauer

发明人： Bruce C. Fleischhauer

IPC分类号： H01L21/306 ,  H01L21/28

CPC分类号： H01L25/0657 ,  A61N1/056 ,  A61N1/362 ,  A61N1/375 ,  A61N1/3962 ,  H01L21/76898 ,  H01L23/3192 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2223/54433 ,  H01L2223/54453 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05673 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure relates to an implantable medical device. The implantable medical device includes a component comprising a first substrate bonded to a second substrate. A method for forming the component includes removing a first portion of tin (Sn) from gold tin (AuSn) through a halogen plasma. A first portion of gold (Au) is exposed in response to removing the first portion of the Sn. The first portion of the Au through a wet etch. A second portion of the Sn is exposed in response to removing the first portion of Au.

摘要翻译： 本公开涉及可植入医疗装置。 该可植入医疗装置包括一个部件，该部件包括与第二基底结合的第一基底。 形成该组件的方法包括通过卤素等离子体从金锡（AuSn）中除去锡（Sn）的第一部分。 金（Au）的第一部分响应于去除Sn的第一部分而暴露。 通过湿蚀刻去除Au的第一部分。 响应于去除Au的第一部分而暴露出Sn的第二部分。