公开(公告)号：US09633971B2

公开(公告)日：2017-04-25

申请号：US14796381

申请日：2015-07-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03009 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/11442 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11614 ,  H01L2224/1162 ,  H01L2224/1182 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13309 ,  H01L2224/13311 ,  H01L2224/13313 ,  H01L2224/13339 ,  H01L2224/13344 ,  H01L2224/13355 ,  H01L2224/13409 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13813 ,  H01L2224/13839 ,  H01L2224/13844 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16104 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16501 ,  H01L2224/81193 ,  H01L2224/81204 ,  H01L2224/81801 ,  H01L2224/8184 ,  H01L2224/83815 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2924/3841 ,  H01L2924/013

Abstract: A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers.

公开(公告)号：US09583417B2

公开(公告)日：2017-02-28

申请号：US14206756

申请日：2014-03-12

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Cyprian Emeka Uzoh ,  Yong Chen

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/498

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/5384 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

Abstract translation: 公开了一般涉及基板的装置。 在这种装置中，衬底具有与第一表面相对的第一表面和第二表面。 第一表面和第二表面限定基底的厚度。 通孔结构从衬底的第一表面延伸到衬底的第二表面。 通孔结构具有位于第一表面处或靠近第一表面的第一端子和位于第二表面处或靠近第二表面处的第二端子，该第二端子由从第一端子延伸到第二端子的通孔结构的导电构件提供。 通孔结构的阻挡层设置在导电部件的至少一部分和基板之间。 阻挡层具有被配置为当信号通过通孔结构的导电构件时抵消导电构件和衬底之间的电容的导电性。

公开(公告)号：US09558964B2

公开(公告)日：2017-01-31

申请号：US14524280

申请日：2014-10-27

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Michael Newman ,  Terrence Caskey

IPC: H01L21/56 ,  H01L23/48 ,  H01L21/48 ,  H05K1/02 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/80 ,  H01L24/81 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14636 ,  H01L27/1469 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2221/68381 ,  H01L2224/13 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K1/0298 ,  H01L2224/81 ,  H01L2924/00

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract translation: 提供了包括电介质区域，多个导电元件，密封剂和微电子元件的微电子组件。 密封剂可以具有不大于与电介质区域或微电子元件中的至少一个相关联的CTE的两倍的热膨胀系数（CTE）。

公开(公告)号：US20160329290A1

公开(公告)日：2016-11-10

申请号：US15212603

申请日：2016-07-18

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Michael Newman ,  Terrence Caskey

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

Abstract translation: 本文公开了微电子组件及其制造方法。 在一个实施例中，形成微电子组件的方法包括组装第一和第二部件以使第一和第二部件的第一主表面彼此面对并且彼此隔开预定间隔，第一部件具有第一和第二相对 主表面，在第一和第二主表面之间沿第一方向延伸的第一厚度和在第一主表面处的多个第一金属连接元件，第二部件在第一主要部分具有多个第二金属连接元件 第二部件的表面; 以及电镀多个金属连接器区域，每个金属连接器区域在第一方向上在相应的第一连接元件和与相应的第一连接元件相对的相应的第二连接元件之间连续延伸。

公开(公告)号：US20160307824A1

公开(公告)日：2016-10-20

申请号：US14686671

申请日：2015-04-14

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5387 ,  H05K1/0203 ,  H05K1/0326 ,  H05K2201/062 ,  H05K2201/10378

Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.

Abstract translation: 提出了可以包括多孔聚酰亚胺材料和形成在多孔聚酰亚胺材料中的电极的衬底结构。 在一些实例中，形成衬底的方法可以包括在衬底上沉积阻挡层; 在阻挡层上沉积抗蚀剂; 图案化和蚀刻抗蚀剂; 形成电极; 去除抗蚀剂; 沉积多孔聚酰亚胺气凝胶; 在气凝胶材料上沉积介电层; 抛光插入件的顶侧以露出电极; 以及从所述插入件的底侧移除所述基板。

公开(公告)号：US09455237B2

公开(公告)日：2016-09-27

申请号：US14754293

申请日：2015-06-29

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L21/3213

CPC classification number: H01L24/11 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/0362 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05578 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05664 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.

公开(公告)号：US09443837B2

公开(公告)日：2016-09-13

申请号：US14709011

申请日：2015-05-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Cyprian Emeka Uzoh

IPC: H01L25/00 ,  H01L23/532 ,  H01L21/50 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/53209 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/808 ,  H01L2224/8385 ,  H01L2224/8389 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/013 ,  H01L2924/15311 ,  H01L2924/2064

Abstract: An assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact electrically coupled with the terminal. A first element has a first surface facing the first surface of the substrate, a first conductor at the first surface and a second conductor at a second surface. An interconnect structure may extend through the first element electrically coupling the first and second conductors. An adhesive layer may bond first surfaces of the first element and the substrate, and at least portions of the first conductor and the substrate conductor may be beyond an edge of the adhesive layer. A continuous electroless plated metal region may extend between the first conductor and the substrate conductor.

Abstract translation: 组件包括具有衬底导体的衬底和在第一表面处的接触件和在第二表面处的端子，用于将组件与组件外部的部件电互连，衬底导体或接触件中的至少一个与电连接 终奌站。 第一元件具有面向基板的第一表面的第一表面，在第一表面处的第一导体和在第二表面处的第二导体。 互连结构可以延伸穿过第一元件电耦合第一和第二导体。 粘合剂层可以粘合第一元件和基底的第一表面，并且第一导体和基底导体的至少一部分可以超出粘合剂层的边缘。 连续的无电镀金属区域可以在第一导体和衬底导体之间延伸。

公开(公告)号：US09412646B2

公开(公告)日：2016-08-09

申请号：US14605654

申请日：2015-01-26

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/15 ,  H01L23/498 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L21/76805 ,  H01L21/02107 ,  H01L21/486 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49827 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An opening such as a small-diameter via is formed in a semiconductor substrate such as a monocrystalline silicon chip or wafer by a high etch rate process which leaves the opening with a rough interior surface. A smoothing layer such as a polysilicon layer is applied over the interior surfaces of the openings. The smoothing layer presents a surface smoother than the original interior surface. An insulating layer is formed over the smoothing layer or formed from the smoothing layer, and a conductive element such as a metal is formed in the opening. In a variant, a glass-forming material such as BPSG is applied in the opening. The glass-forming material is reflowed to form a glassy insulating layer which presents a smooth surface. The interface between the metal conductive element and the insulating or glassy layer is smooth, which improves mechanical and electrical properties.

公开(公告)号：US09368479B2

公开(公告)日：2016-06-14

申请号：US14201585

申请日：2014-03-07

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Arkalgud R. Sitaram ,  Cyprian Emeka Uzoh

IPC: H01L23/42 ,  H01L25/065 ,  H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

Abstract translation: 装置一般涉及三维堆叠集成电路。 在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。 第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。 所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。 衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。 所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。

公开(公告)号：US20160049383A1

公开(公告)日：2016-02-18

申请号：US14532806

申请日：2014-11-04

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Hong Shen ,  Christopher W. Lattin ,  Guilian Gao ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/11003 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14181 ,  H01L2224/14517 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2224/17519 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/185 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A device and method for an integrated device includes a first redistribution layer comprising one or more first conductors, one or more first dies mounted to a first surface of the first redistribution layer and electrically coupled to the first conductors, one or more first posts having first ends attached to the first dies and second ends opposite the first ends, one or more second posts having third ends attached to the first surface of the first redistribution layer and fourth ends opposite the third ends, and a second redistribution layer comprising one or more second conductors, the second redistribution layer being attached to the second ends of the first posts and to the fourth ends of the second posts. In some embodiments, the integrated device further includes a heat spreader mounted to a second surface of the first redistribution layer. The second surface is opposite the first surface.

Abstract translation: 一种用于集成器件的器件和方法包括：第一再分配层，其包括一个或多个第一导体，一个或多个第一裸片，其安装到第一再分布层的第一表面并电耦合到第一导体，一个或多个第一柱具有第一导体 末端附接到第一模具和与第一端相对的第二端，一个或多个第二柱，其具有附接到第一再分布层的第一表面的第三端和与第三端相对的第四端，以及包括一个或多个第二端的第二再分布层 导体，第二再分布层附接到第一柱的第二端和第二柱的第四端。 在一些实施例中，集成装置还包括安装到第一再分配层的第二表面的散热器。 第二表面与第一表面相对。