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公开(公告)号：US20170359897A1
公开(公告)日：2017-12-14
申请号：US15620866
申请日：2017-06-13
Applicant: Infineon Technologies Austria AG
Inventor： Frank Pueschner , Peter Stampka , Jens Pohl , Marcus Janke
CPC classification number: H05K1/181 , G06K19/07722 , G06K19/07733 , G06K19/07737 , G06K19/07739 , G06K19/07741 , G06K19/07747 , G06K19/07766 , G06K19/07773 , H01R12/714 , H05K1/0275 , H05K1/11 , H05K1/113 , H05K3/4007 , H05K3/4608 , H05K3/4694 , H05K2201/086 , H05K2201/09409 , H05K2201/09445 , H05K2201/09663 , H05K2201/10098 , H05K2201/10719
Abstract: In various embodiments, a chip card module is provided. The chip card module includes a chip card module contact array having six contact pads that are arranged in two rows having three contact pads each in accordance with ISO 7816, and three additional contact pads that are arranged between the two rows. Each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows.
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公开(公告)号：US20170047672A1
公开(公告)日：2017-02-16
申请号：US15220575
申请日：2016-07-27
Applicant: FUJITSU LIMITED
Inventor： YOSHIHIRO MORITA
CPC classification number: H05K1/0243 , H05K2201/10325 , H05K2201/10356 , H05K2201/10719
Abstract: A contactor coupled to an electrode of a semiconductor package mounted on a mounting surface of a wiring board, the contactor includes: a cable including a core line; a connector attached to a front end of the cable, and to be inserted into a through hole that penetrates the wiring board in a thickness direction thereof; and a signal land formed on a front end surface of the connector, and electrically coupled with the core line.
Abstract translation: 一种接触器，其耦合到安装在布线板的安装表面上的半导体封装的电极，所述接触器包括：包括芯线的电缆; 连接器，其连接到所述电缆的前端，并插入到贯穿所述布线板的厚度方向的通孔中; 以及形成在连接器的前端表面上并与芯线电耦合的信号接合面。
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公开(公告)号：US09565755B2
公开(公告)日：2017-02-07
申请号：US15062477
申请日：2016-03-07
Applicant: FUJITSU LIMITED
Inventor： Teru Nakanishi , Nobuyuki Hayashi , Masaru Morita , Yasuhiro Yoneda
CPC classification number: H05K1/0296 , H01L23/13 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/4985 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05647 , H01L2224/1379 , H01L2224/13839 , H01L2224/13847 , H01L2224/16225 , H01L2224/16235 , H01L2224/81193 , H01L2224/81801 , H01L2924/01004 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/15311 , H05K1/181 , H05K3/3436 , H05K2201/10287 , H05K2201/10378 , H05K2201/10424 , H05K2201/10719 , Y02P70/613 , H01L2924/00
Abstract: A semiconductor device includes: a wiring board including a first electrode pad on a surface thereof; a circuit board disposed to stand on the wiring board, and including an interconnection connected to the first electrode pad; and a semiconductor package disposed to face the wiring board with the circuit board interposed therebetween, and including a second electrode pad on a surface thereof, the second electrode pad being connected to the interconnection.
Abstract translation: 半导体器件包括：布线板，其表面上包括第一电极焊盘; 电路板，被布置成站立在所述布线板上，并且包括连接到所述第一电极焊盘的互连; 以及半导体封装，其设置成与所述布线板面对所述电路板，并且在其表面上包括第二电极焊盘，所述第二电极焊盘连接到所述互连。
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公开(公告)号：US09538636B1
公开(公告)日：2017-01-03
申请号：US13803081
申请日：2013-03-14
Applicant: MACOM Technology Solutions Holdings, Inc.
Inventor： Christopher D. Weigand , Andrzej Rozbicki
CPC classification number: H05K1/181 , H01L23/13 , H01L23/14 , H01L23/49805 , H01L23/49822 , H05K1/0201 , H05K1/0251 , H05K1/0306 , H05K1/115 , H05K1/14 , H05K1/141 , H05K1/18 , H05K3/0097 , H05K3/429 , H05K2201/041 , H05K2201/066 , H05K2201/09181 , H05K2201/09509 , H05K2201/09854 , H05K2201/10719
Abstract: An apparatus having a plurality of insulating layers, a plurality of conductive layers and a plating is disclosed. The conductive layers may be separated by the insulating layers. A first pattern in a first of the conductive layers generally extends to an edge castellation. A second pattern in a second of the conductive layers may also extends to the edge castellation. The plating may be disposed in the edge castellation and connect the first pattern to the second pattern. The plating in the castellation may extend at most between a subset of the conductive layers.
Abstract translation: 公开了一种具有多个绝缘层，多个导电层和电镀层的装置。 导电层可以被绝缘层分离。 第一导电层中的第一图案通常延伸到边缘星座。 在第二导电层中的第二图案也可以延伸到边缘星座。 电镀可以设置在边缘地毯中并且将第一图案连接到第二图案。 地板中的电镀最多可以在导电层的子集之间延伸。
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15.发明申请ELECTRONIC COMPONENT HAVING FUNCTION TO DETECT MANUFACTURING DEFECTS OR DAMAGE/DEGRADATION AND PRINTED WIRING BOARD 审中-公开具有检测制造缺陷或损坏/降解和印刷线路板的功能的电子元件公开(公告)号：US20160349307A1
公开(公告)日：2016-12-01
申请号：US15166216
申请日：2016-05-26
Applicant: FANUC Corporation
Inventor： Takaaki KOMATSU , Yasumichi SAKODA
CPC classification number: H03K19/20 , G01R31/2812 , H01L22/32 , H01L22/34 , H01L2224/131 , H01L2224/16227 , H05K3/3436 , H05K2201/10719 , H05K2201/10734 , H05K2203/162 , H01L2924/014
Abstract: An electronic component having a plurality of terminals arranged on a bottom side of a package and mounted on a printed wiring board includes at least one detection terminal as a portion of the plurality of terminals, the detection terminal being connected to a ground outside the electronic component, wherein the detection terminal is connected to an input port of an input buffer and one end of a resistor inside the electronic component, the other end of the resistor is connected to a power supply, and the input buffer detects a poor connection of a solder joint or a socket by outputting a first binary signal obtained by binarizing a voltage level input into the input buffer using a predetermined threshold.
Abstract translation: 具有布置在封装的底侧并安装在印刷布线板上的多个端子的电子部件包括至少一个检测端子作为多个端子的一部分，检测端子连接到电子部件外部的接地 其特征在于，所述检测端子与所述电子部件的输入缓冲器的输入端口和所述电阻器的一端连接，所述电阻器的另一端与电源连接，所述输入缓冲器检测焊料的连接不良 通过输出通过使用预定阈值将输入到输入缓冲器的电压电平二值化而获得的第一二进制信号来连接或插座。
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Patent Agency Ranking
公开(公告)号：US20160309592A1
公开(公告)日：2016-10-20
申请号：US15099905
申请日：2016-04-15
Applicant: Rohm Co., Ltd.
Inventor： Masashi Nagasato
CPC classification number: H05K1/0243 , H05K1/0242 , H05K1/025 , H05K3/4685 , H05K2201/09154 , H05K2201/09609 , H05K2201/09618 , H05K2201/09727 , H05K2201/09736 , H05K2201/10053 , H05K2201/1009 , H05K2201/10704 , H05K2201/10719 , H05K2201/10734
Abstract: A printed wiring board used to suppress parasitic component is provided. The printed wiring board 100 includes a multi-layer substrate 110, and a power line 50 laid on the multi-layer substrate 110 and connected with a power terminal row T11a-T11d of a semiconductor device 10. The power line 50 includes a first wiring pattern 51 formed on a surface of the multi-layer substrate 110, a second wiring pattern 52 formed within the multi-layer substrate 110, and interlayer connections 53x and 53y electrically conducting the first wiring pattern 51 and the second wiring pattern 52 to bypass at least a portion of the power terminal row T11a-T11d.
Abstract translation: 提供了用于抑制寄生成分的印刷线路板。 印刷电路板100包括多层基板110和布置在多层基板110上并与半导体装置10的电源端子排T11a-T11d连接的电力线50.电力线50包括第一布线 形成在多层基板110的表面上的图案51，形成在多层基板110内的第二布线图案52，以及导电第一布线图案51和第二布线图案52旁路的层间连接53x和53y 电力端子排T11a-T11d的至少一部分。
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17.发明申请SEMICONDUCTOR PACKAGE MODULES, MEMORY CARDS INCLUDING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权半导体封装模块，包括其的存储卡，以及包括其的电子系统公开(公告)号：US20160295698A1
公开(公告)日：2016-10-06
申请号：US14813359
申请日：2015-07-30
Applicant: SK hynix Inc.
Inventor： Jung Tae JEONG
CPC classification number: H05K1/181 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/73 , H01L2224/13101 , H01L2224/16225 , H01L2224/32225 , H01L2224/45139 , H01L2224/45144 , H01L2224/45147 , H01L2224/73204 , H01L2924/15174 , H01L2924/181 , H01L2924/19107 , H05K3/3436 , H05K2201/10287 , H05K2201/10719 , H05K2201/10727 , H05K2203/049 , Y02P70/613 , H01L2924/00012 , H01L2924/014 , H01L2924/00014
Abstract: A semiconductor package module may include a first substrate, and a second substrate disposed to face the first substrate. The semiconductor package module may include an interconnection member electrically connecting the first substrate to the second substrate and including a plurality of wires. Portions of the plurality of wires may be twisted and wound together and may be bent to extend in a predetermined direction.
Abstract translation: 半导体封装模块可以包括第一衬底和布置成面对第一衬底的第二衬底。 半导体封装模块可以包括将第一衬底电连接到第二衬底并且包括多个电线的互连构件。 多个线的一部分可以被扭绞并缠绕在一起，并且可以被弯曲以沿预定方向延伸。
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公开(公告)号：US20160165724A1
公开(公告)日：2016-06-09
申请号：US15045024
申请日：2016-02-16
Applicant: Kevin E. Wells , Richard C. Stamey
Inventor： Kevin E. Wells , Richard C. Stamey
CPC classification number: H05K1/115 , G06F1/16 , G06F1/18 , G06F1/183 , H01L23/49833 , H01L2924/0002 , H05K1/141 , H05K3/3436 , H05K3/421 , H05K2201/041 , H05K2201/10719 , Y02P70/613 , Y10T29/49128 , H01L2924/00
Abstract: Modular printed circuit board (PCB) structures and methods of producing them are described herein. In some embodiments, a PCB structure may include a first PCB module including first structures on one or more layers of the first PCB module. The PCB structure may further include a second PCB module including second structures on one or more layers of the second PCB module. The PCB structure may additionally include a middle layer between the first PCB module and the second PCB module. The middle layer electrically coupling, without connectors, one or more of the first structures aligned with one or more of the second structures.
Abstract translation: 本文描述了模块化印刷电路板（PCB）结构及其制造方法。 在一些实施例中，PCB结构可以包括第一PCB模块，其包括在第一PCB模块的一个或多个层上的第一结构。 PCB结构还可以包括第二PCB模块，其包括在第二PCB模块的一个或多个层上的第二结构。 PCB结构还可以包括在第一PCB模块和第二PCB模块之间的中间层。 中间层电耦合，没有连接器，一个或多个第一结构与一个或多个第二结构对准。
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公开(公告)号：US09320144B2
公开(公告)日：2016-04-19
申请号：US13319158
申请日：2010-06-15
Applicant: James Rathburn
Inventor： James Rathburn
CPC classification number: H05K1/141 , H01R12/52 , H01R12/57 , H05K3/3436 , H05K2201/0311 , H05K2201/049 , H05K2201/10295 , H05K2201/10719 , Y10T29/49139 , Y10T29/49147
Abstract: A semiconductor socket including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact members are located in the plurality of the through holes. The plurality of contact members each include a proximal end accessible from the second surface, and a distal end extending above the first surface. At least one dielectric layer is bonded to the second surface of the substrate with recesses corresponding to target circuit geometry. A conductive material deposited in at least a portion of the recesses to form conductive traces redistributing terminal pitch of the proximal ends of the contact members.
Abstract translation: 一种半导体插座，包括具有从第一表面延伸到第二表面的多个通孔的基板。 多个离散接触构件位于多个通孔中。 多个接触构件各自包括可从第二表面接近的近端和在第一表面上方延伸的远端。 至少一个电介质层与基板的第二表面结合，其凹部对应于目标电路几何形状。 沉积在至少一部分凹陷中的导电材料以形成重新分布接触构件的近端的端子间距的导电迹线。
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20.发明申请公开(公告)号：US20150255383A1
公开(公告)日：2015-09-10
申请号：US14636850
申请日：2015-03-03
Applicant: CANON KABUSHIKI KAISHA
Inventor： Ichiro Kataoka , Osamu Hamamoto , Kazuya Notsu , Koji Tamura , Kunihiko Minegishi
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49838 , H01L23/49811 , H01L23/49866 , H01L24/48 , H01L24/85 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/15153 , H01L2924/15173 , H01L2924/15174 , H01L2924/15184 , H01L2924/15313 , H01L2924/16195 , H01L2924/181 , H05K1/0204 , H05K1/111 , H05K3/3436 , H05K2201/094 , H05K2201/09781 , H05K2201/10719 , H05K2201/10727 , H05K2203/0465 , H01L2224/45099 , H01L2924/00012
Abstract: A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion.
Abstract translation: 安装构件包括多个内部连接部分，每个内部连接部分电连接到电子设备，以及多个外部连接部分，每个外部连接部分被焊接，其中多个外部连接部分包括连通的第一连接部分 与多个内部连接部分中的至少任一个以及与第一连接部分不同的第二连接部分，并且第一连接部分和第二连接部分的表面包括金层，并且第二连接部分的金层的厚度 连接部分小于第一连接部分的金层的厚度。
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