公开(公告)号：US20140264786A1

公开(公告)日：2014-09-18

申请号：US14292925

申请日：2014-06-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/522 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/30 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13157 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2224/19 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die with a sloped side surface. The first semiconductor die is mounted to a temporary carrier. An RDL extends from a back surface of the first semiconductor die along the sloped side surface of the first semiconductor die to the carrier. An encapsulant is deposited over the carrier and a portion of the RDL along the sloped side surface. The back surface of the first semiconductor die and a portion of the RDL is devoid of the encapsulant. The temporary carrier is removed. An interconnect structure is formed over the encapsulant and exposed active surface of the first semiconductor die. The RDL is electrically connected to the interconnect structure. A second semiconductor die is mounted over the back surface of the first semiconductor die. The second semiconductor die has bumps electrically connected to the RDL.

Abstract translation: 半导体器件具有具有倾斜侧表面的第一半导体管芯。 第一半导体管芯安装到临时载体上。 RDL从第一半导体管芯的后表面沿着第一半导体管芯的倾斜侧表面延伸到载体。 密封剂沉积在载体上，RDL的一部分沿着倾斜的侧表面沉积。 第一半导体管芯的背面和RDL的一部分没有密封剂。 移除临时载体。 在第一半导体管芯的密封剂和暴露的有源表面上形成互连结构。 RDL电连接到互连结构。 第二半导体管芯安装在第一半导体管芯的后表面上。 第二半导体管芯具有与RDL电连接的突起。

公开(公告)号：US20140070427A1

公开(公告)日：2014-03-13

申请号：US14082155

申请日：2013-11-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/80 ,  H01L24/96 ,  H01L25/0657 ,  H01L2224/0231 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/03901 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05562 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16225 ,  H01L2224/24 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/82 ,  H01L2224/821 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2224/03 ,  H01L2224/80 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.

Abstract translation: 半导体器件具有安装到载体上的多个半导体管芯。 密封剂沉积在载体周围的半导体管芯的周边区域上。 通过密封剂形成多个通孔。 第一导电层保形地施加在通孔的侧壁上以形成导电通孔。 在半导体管芯的导电通孔和接触焊盘之间的半导体管芯的第一表面上形成第二导电层。 第一和第二导电层可以在相同的制造过程中形成。 在半导体管芯的与半导体管芯的第一表面相对的第二表面上形成第三导电层。 第三导电层电连接到导电通孔。 多个半导体管芯通过导电通孔和第二和第三导电层堆叠并电连接。

公开(公告)号：US20140008769A1

公开(公告)日：2014-01-09

申请号：US14021206

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L25/00

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

Abstract translation: 半导体晶片具有多个具有应力敏感区域的第一半导体管芯。 掩模层或屏幕设置在应力敏感区域上方。 底部填充材料沉积在晶片上。 掩蔽层或屏幕防止邻近敏感区域形成底部填充材料。 去除掩模层或屏幕，留下邻近敏感区域的底部填充材料中的空腔。 将半导体晶片分割成第一模具。 第一管芯可以安装到堆积互连结构或第二半导体管芯，其中空腔分离敏感区域并建立互连结构或第二管芯。 在第一和第二管芯之间形成接合线，并且密封剂沉积在第一和第二管芯和接合线上。 可以通过第一或第二管芯形成导电通孔。

公开(公告)号：US20130241080A1

公开(公告)日：2013-09-19

申请号：US13887180

申请日：2013-05-03

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/561 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/83 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/95121 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/115 ,  H05K3/429 ,  H05K3/4647 ,  H05K2201/09518 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/03

Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Abstract translation: 半导体器件具有在衬底上形成多个导电通孔和导电层的衬底。 半导体管芯安装在载体上。 衬底被安装到与载体相对的半导体管芯上。 在半导体管芯周围的衬底和载体之间沉积密封剂。 通过衬底和密封剂形成多个导电TMV。 导电TMV从密封剂突出以帮助互连结构的对准。 导电TMV电连接到导电层和导电通孔。 移除载体并且在与衬底相对的密封剂和半导体管芯的表面上形成互连结构。 互连结构电连接到导电TMV。 多个半导体器件可以通过衬底层叠并电连接，导电TMV和互连结构。

公开(公告)号：US20130154067A1

公开(公告)日：2013-06-20

申请号：US13765594

申请日：2013-02-12

Applicant: Stats ChipPac, Ltd.

Inventor： Reza A. Pagaila ,  KiYoun Jang ,  HunTeak Lee

IPC: H01L23/495

CPC classification number: H01L23/4952 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/05082 ,  H01L2224/05111 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32057 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a vertically offset BOT interconnect structure. The vertical offset is achieved with a leadframe having a plurality of lead fingers around a die paddle. A first conductive layer is formed over the lead fingers. A second conductive layer is formed over the lead fingers. Each second conductive layer is positioned adjacent to the first conductive layer and each first conductive layer is positioned adjacent to the second conductive layer. The second conductive layer has a height greater than a height of the first conductive layer. The first and second conductive layers can have a side-by-side arrangement or staggered arrangement. Bumps are formed over the first and second conductive layers. Bond wires are electrically connected to the bumps. A semiconductor die is mounted over the die paddle of the leadframe and electrically connected to the bond wires and BOT interconnect structure.

Abstract translation: 半导体器件具有垂直偏移的BOT互连结构。 垂直偏移通过引线框架实现，引线框架具有围绕模板的多个引线。 在引线指上形成第一导电层。 在引线指上形成第二导电层。 每个第二导电层定位成与第一导电层相邻，并且每个第一导电层定位成与第二导电层相邻。 第二导电层的高度大于第一导电层的高度。 第一和第二导电层可以具有并排布置或交错布置。 在第一和第二导电层上形成凸起。 接合线电连接到凸块。 半导体管芯安装在引线框架的管芯上并电连接到接合线和BOT互连结构。

公开(公告)号：US20130140683A1

公开(公告)日：2013-06-06

申请号：US13726467

申请日：2012-12-24

Applicant: STATS CHIPPAC, LTD.

Inventor： Reza A. Pagaila

IPC: H01L23/522 ,  H01L23/34 ,  H01L21/768 ,  H01L23/552

CPC classification number: H01L23/522 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/81805

Abstract: In a semiconductor device, a first semiconductor die is mounted with its active surface oriented to a temporary carrier. An encapsulant is deposited over the first semiconductor die and temporary carrier. The temporary carrier is removed to expose a first side of the encapsulant and active surface of the first semiconductor die. A masking layer is formed over the active surface of the first semiconductor die. A first interconnect structure is formed over the first side of the encapsulant. The masking layer blocks formation of the first interconnect structure over the active surface of the first semiconductor die. The masking layer is removed to form a cavity over the active surface of the first semiconductor die. A second semiconductor die is mounted in the cavity. The second semiconductor die is electrically connected to the active surface of the first semiconductor die with a short signal path.

Abstract translation: 在半导体器件中，第一半导体管芯被安装成其有源表面定向到临时载体。 密封剂沉积在第一半导体管芯和临时载体上。 去除临时载体以暴露第一半导体管芯的密封剂和有源表面的第一侧。 在第一半导体管芯的有源表面上形成掩模层。 在密封剂的第一侧上形成第一互连结构。 掩模层阻止在第一半导体管芯的有效表面上形成第一互连结构。 去除掩模层以在第一半导体管芯的有效表面上形成空腔。 第二半导体管芯安装在腔中。 第二半导体管芯通过短信号路径电连接到第一半导体管芯的有源表面。

公开(公告)号：US20130087897A1

公开(公告)日：2013-04-11

申请号：US13691440

申请日：2012-11-30

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Nathapong Suthiwongsunthorn

IPC: H01L23/552

CPC classification number: H01L23/552 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/85 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers.

公开(公告)号：US09679881B2

公开(公告)日：2017-06-13

申请号：US14021206

申请日：2013-09-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/563 ,  H01L23/315 ,  H01L23/66 ,  H01L24/73 ,  H01L25/00 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A semiconductor wafer has a plurality of first semiconductor die with a stress sensitive region. A masking layer or screen is disposed over the stress sensitive region. An underfill material is deposited over the wafer. The masking layer or screen prevents formation of the underfill material adjacent to the sensitive region. The masking layer or screen is removed leaving a cavity in the underfill material adjacent to the sensitive region. The semiconductor wafer is singulated into the first die. The first die can be mounted to a build-up interconnect structure or to a second semiconductor die with the cavity separating the sensitive region and build-up interconnect structure or second die. A bond wire is formed between the first and second die and an encapsulant is deposited over the first and second die and bond wire. A conductive via can be formed through the first or second die.

公开(公告)号：US09679824B2

公开(公告)日：2017-06-13

申请号：US13845542

申请日：2013-03-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Rajendra D. Pendse ,  Jun Mo Koo

IPC: H01L23/52 ,  H01L23/28 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/28 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/18 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155

Abstract: A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer.

公开(公告)号：US09530738B2

公开(公告)日：2016-12-27

申请号：US14462347

申请日：2014-08-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Linda Pei Ee Chua ,  Byung Tai Do ,  Reza A. Pagaila

IPC: H01L23/48 ,  H01L23/02 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L23/00 ,  H01L25/03 ,  H01L25/00 ,  H01L23/552 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/288 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/78 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/52 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/17 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L29/40 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/20 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32502 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has conductive pillars formed over a carrier. A first semiconductor die is mounted over the carrier between the conductive pillars. An encapsulant is deposited over the first semiconductor die and carrier and around the conductive pillars. A recess is formed in a first surface of the encapsulant over the first semiconductor die. The recess has sloped or stepped sides. A first interconnect structure is formed over the first surface of the encapsulant. The first interconnect structure follows a contour of the recess in the encapsulant. The carrier is removed. A second interconnect structure is formed over a second surface of the encapsulant and first semiconductor die. The first and second interconnect structures are electrically connected to the conductive pillars. A second semiconductor die is mounted in the recess. A third semiconductor die is mounted over the recess and second semiconductor die.