公开(公告)号：US20090203170A1

公开(公告)日：2009-08-13

申请号：US11914416

申请日：2006-03-30

Applicant: Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

Inventor： Seiichi Nakatani ,  Seiji Karashima ,  Takashi Kitae ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC: H01L21/60 ,  B23P19/00

CPC classification number: H01L21/563 ,  H01L21/67103 ,  H01L21/67126 ,  H01L23/3135 ,  H01L24/11 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/743 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75743 ,  H01L2224/81121 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/8192 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83886 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/381 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/0126 ,  H05K2203/082 ,  Y02P70/613 ,  Y10T29/53183 ,  H01L2924/00 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/00015 ,  H01L2924/0665 ,  H01L2924/0695 ,  H01L2224/05599

Abstract: A flip chip mounting method includes holding a circuit board (213) and a semiconductor chip (206), aligning the circuit board (213) with the semiconductor chip (206) while holding them with a predetermined gap therebetween, heating the circuit board (213) or the semiconductor chip (206) to a temperature at which solder powder in a solder resin composition (216) formed of solder powder (214) and a resin (215) is melted, supplying the solder resin composition (216) by a capillary phenomenon, and curing the resin (215), wherein the melted solder powder (214) in the solder resin composition (216) is moved through the predetermined gap across which the circuit board (213) and the semiconductor chip (206) are held, and self-assembled and grown, whereby the connection terminals (211) and the electrode terminals (207) are connected to each other electrically. According to this configuration, a flip chip mounting method having high productivity and reliability, which enables a next generation semiconductor chip to be mounted on a circuit board, a mounted body thereof, and a mounting apparatus thereof are provided.

Abstract translation: 一种倒装芯片安装方法，包括保持电路板（213）和半导体芯片（206），使电路板（213）与半导体芯片（206）保持一定间隔，同时将电路板（213）加热 ）或半导体芯片（206）的温度升高到由焊料粉末（214）和树脂（215）形成的焊料树脂组合物（216）中的焊料粉末熔化的温度，通过毛细管 现象，固化树脂（215），其中焊料树脂组合物（216）中的熔融焊料粉末（214）移动通过保持电路板（213）和半导体芯片（206）的预定间隙， 并且自组装和生长，由此连接端子（211​​）和电极端子（207）彼此电连接。 根据该结构，提供了一种能够将下一代半导体芯片安装在电路板上的高生产率和可靠性的倒装芯片安装方法及其安装体及其安装装置。

公开(公告)号：US07547968B2

公开(公告)日：2009-06-16

申请号：US11434745

申请日：2006-05-17

Applicant: Takahiro Sugimura ,  Satoshi Imasu ,  Norihiko Sugita ,  Takafumi Betsui

Inventor： Takahiro Sugimura ,  Satoshi Imasu ,  Norihiko Sugita ,  Takafumi Betsui

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2225/1005 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49128 ,  Y10T29/53178 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2924/0695

Abstract: The reliability of a semiconductor device which has the semiconductor components which were mounted on the same surface of the same substrate via the bump electrodes with which height differs, and with which package structure differs is improved. Semiconductor component 2 of WPP structure is mounted on the main surface of the interposer substrate which forms a semiconductor device via a plurality of bump electrodes. Semiconductor component 3 of CSP structure is mounted on the main surface of an interposer substrate via a plurality of bump electrodes with larger diameter and contiguity pitch than the above-mentioned bump electrode. And under-filling 4a and 4b mutually different, are filled up between the facing surfaces of this interposer substrate and semiconductor components 2 , and between the facing surfaces of the interposer substrate and semiconductor components 3, respectively.

Abstract translation: 具有半导体元件的半导体器件的可靠性提高了通过高度不同的突起电极安装在同一基板的同一表面上的半导体器件的可靠性。 WPP结构的半导体部件2通过多个凸块电极安装在形成半导体器件的插入器基板的主表面上。 CSP结构的半导体部件3通过多个比上述凸起电极具有更大的直径和邻接间距的凸起电极安装在插入基片的主表面上。 并且相互不同的不充分的4a和4b分别填充在该插入器基板和半导体部件2的相对表面之间以及插入器基板和半导体部件3的相对表面之间。

公开(公告)号：US07528460B2

公开(公告)日：2009-05-05

申请号：US11414485

申请日：2006-05-01

Applicant: Takao Nishimura ,  Tetsuya Hiraoka

Inventor： Takao Nishimura ,  Tetsuya Hiraoka

IPC: H01L29/00 ,  H01L23/495 ,  H01L23/02

CPC classification number: H01L23/49589 ,  H01L23/49503 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L25/16 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/0695

Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

Abstract translation: 一种半导体器件，其能够防止电极端子与芯片焊盘之间的接触，并且能够可靠地对电极端子进行引线接合。 无源部件形成为使得每个电极端子的垂直高度高于元件部件的垂直高度。 更具体地，电极端子的每个横截面面积略大于元件部分的横截面面积。 因此，每个电极端子的上部和下部略高于（突出）元件部分。 通过粘合剂固定无源部件，使得元件部分位于高位置部分上，以便几乎平行于基板表面。 此外，每个电极端子（底部）的一部分位于凹部内的每个空间中。 因此，在每个电极端子和管芯焊盘之间形成预定的空间。

公开(公告)号：US20080150157A1

公开(公告)日：2008-06-26

申请号：US11868036

申请日：2007-10-05

Applicant: Takao NISHIMURA ,  Yoshiaki NARISAWA

Inventor： Takao NISHIMURA ,  Yoshiaki NARISAWA

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/26145 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83051 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/0695 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/013

Abstract: A semiconductor device, includes a wiring board; a first semiconductor element mounted on the wiring board; a second semiconductor element mounted on the first semiconductor element so that a position of the second semiconductor element is shifted relative to a position of the first semiconductor element; wherein a part of a main surface of the second semiconductor element faces the first semiconductor element; and an electrode pad provided on the main surface of the second semiconductor element is connected to a second semiconductor element connection pad of the wiring board by a connection part.

Abstract translation: 一种半导体器件，包括布线板; 安装在所述布线板上的第一半导体元件; 安装在所述第一半导体元件上的第二半导体元件，使得所述第二半导体元件的位置相对于所述第一半导体元件的位置移位; 其中所述第二半导体元件的主表面的一部分面向所述第一半导体元件; 并且设置在第二半导体元件的主表面上的电极焊盘通过连接部分连接到布线板的第二半导体元件连接焊盘。

公开(公告)号：US20070170600A1

公开(公告)日：2007-07-26

申请号：US11414485

申请日：2006-05-01

Applicant: Takao Nishimura ,  Tetsuya Hiraoka

Inventor： Takao Nishimura ,  Tetsuya Hiraoka

IPC: H01L21/44

CPC classification number: H01L23/49589 ,  H01L23/49503 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L25/16 ,  H01L2224/27013 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/92247 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01026 ,  H01L2924/00 ,  H01L2924/0665 ,  H01L2924/0695

Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.

Abstract translation: 一种半导体器件，其能够防止电极端子与芯片焊盘之间的接触，并且能够可靠地对电极端子进行引线接合。 无源部件形成为使得每个电极端子的垂直高度高于元件部件的垂直高度。 更具体地，电极端子的每个横截面面积略大于元件部分的横截面面积。 因此，每个电极端子的上部和下部略高于（突出）元件部分。 通过粘合剂固定无源部件，使得元件部分位于高位置部分上，以便几乎平行于基板表面。 此外，每个电极端子（底部）的一部分位于凹部内的每个空间中。 因此，在每个电极端子和管芯焊盘之间形成预定的空间。

公开(公告)号：US20040031545A1

公开(公告)日：2004-02-19

申请号：US10643976

申请日：2003-08-20

Inventor： Kazutaka Okamoto ,  Yasuo Kondo ,  Teruyoshi Abe ,  Yasuhisa Aono ,  Junya Kaneda ,  Ryuichi Saito ,  Yoshihiko Koike

IPC: C22F001/08

CPC classification number: H01L24/32 ,  C22C1/1036 ,  C22C32/0021 ,  C22C32/0036 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4334 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/072 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83455 ,  H01L2224/83805 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/0695 ,  H01L2924/014

Abstract: Provided are a composite material excellent in plastic workability, a method of producing the composite material, a heat-radiating board of a semiconductor equipment, and a semiconductor equipment to which this heat-radiating board is applied. This composite material comprises a metal and an inorganic compound formed to have a dendritic shape or a bar shape. In particular, this composite material is a copper composite material, which comprises 10 to 55 vol.% cuprous oxide (Cu2O) and the balance of copper (Cu) and incidental impurities and has a coefficient of thermal expansion in a temperature range from a room temperature to 300null C. of from 5null10null6 to 17null10null6/null C. and a thermal conductivity of 100 to 380 W/mnullk. This composite material can be produced by a process comprising the steps of melting, casting and working and is applied to a heat-radiating board of a semiconductor article.

Abstract translation: 提供了塑料加工性优异的复合材料，复合材料的制造方法，半导体设备的散热板以及应用该散热板的半导体设备。 该复合材料包括形成为具有树枝状或棒状的金属和无机化合物。 特别地，该复合材料是铜复合材料，其包含10至55体积％的氧化亚铜（Cu 2 O）和余量的铜（Cu）和附带的杂质，并且在室内的温度范围内具有热膨胀系数 温度至300℃，为5×10 -6至17×10 -6 /℃，热导率为100至380W / mk 该复合材料可以通过包括熔融，铸造和加工的步骤的方法制造并施加到半导体制品的散热板上。

公开(公告)号：US20030127712A1

公开(公告)日：2003-07-10

申请号：US10322672

申请日：2002-12-19

Inventor： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsuro Matsumoto

IPC: H01L021/44 ,  H01L023/48

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/0695 ,  H01L2224/85399

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the nullLead-On-Chipnull or nullChip-On-Leadnull structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract translation: 由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。 鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。 在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小 杂散容量，提高信号传输速率和减少电气噪声。

公开(公告)号：US20020025667A1

公开(公告)日：2002-02-28

申请号：US09982748

申请日：2001-10-18

Inventor： Warren M. Farnworth

IPC: H01L021/44 ,  H01L021/48 ,  H01L021/50

CPC classification number: H01L23/4951 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/27 ,  H01L24/29 ,  H01L24/94 ,  H01L29/0657 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05664 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/83191 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/0695

Abstract: A method for forming a semiconductor device includes forming a conductive bump on one or more of bond pads of a semiconductor substrate of a semiconductor wafer. A top or uppermost portion of each conductive bump is then planarized. The exposed portions of an active surface of the semiconductor wafer are filled with a layer of encapsulation material. The conductive bumps are reformed to their preplanarized shape and the semiconductor wafer is then diced to form singulated semiconductor dice. A preferred method of the invention also includes placing each singulated die in a mold to complete a second encapsulation step wherein a layer of encapsulation material is formed on the back surface or, alternatively, on the back and side surfaces of the semiconductor die in order to encapsulate the back, or the back and sides, of the semiconductor die.

Abstract translation: 一种用于形成半导体器件的方法包括在半导体晶片的半导体衬底的一个或多个接合焊盘上形成导电凸块。 然后将每个导电凸块的顶部或最上部分平坦化。 半导体晶片的有源表面的暴露部分填充有一层封装材料。 将导电凸块重新形成其预制的形状，然后切割半导体晶片以形成单个半导体晶片。 本发明的优选方法还包括将每个单个模具放置在模具中以完成第二封装步骤，其中封装材料层形成在半导体管芯的背表面上，或备选地形成在半导体管芯的后表面和侧表面上，以便 封装半导体管芯的背面或背面和侧面。

公开(公告)号：US06330158B1

公开(公告)日：2001-12-11

申请号：US09587610

申请日：2000-06-05

Applicant: Salman Akram

Inventor： Salman Akram

IPC: H05K720

CPC classification number: H01L24/73 ,  H01L23/4334 ,  H01L23/4951 ,  H01L24/29 ,  H01L24/33 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2224/83805 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01055 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/15763 ,  H01L2924/181 ,  H05K1/18 ,  H05K2201/10151 ,  H05K2201/10454 ,  H05K2201/10522 ,  H05K2201/10696 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01032 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/0665 ,  H01L2924/0695 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A semiconductor package includes a semiconductor die, a lead frame wire bonded to the die, and a plastic body encapsulating the die. The package also includes a first heat sink attached to a face of the die, and a second heat sink attached to a back side of the die. Thermally conductive adhesive layers attach the heat sinks to the die, and provide a thermal path therebetween. In addition, the heat sinks project from the plastic body, and have end portions that are sized and shaped to interlock with heat sinks on an adjacent package to form an electronic assembly. In the electronic assembly, the interlocking heat sinks maintain contact surfaces on the heat sinks in physical contact and improve heat dissipation from the packages. An alternate embodiment package includes a thermally conductive encapsulant which attaches a pair of heat sinks, and encapsulates the die.

Abstract translation: 半导体封装包括半导体管芯，结合到管芯的引线框架引线和封装管芯的塑料体。 该包装还包括附接到模具的表面的第一散热器和附接到模具的背面的第二散热器。 导热粘合剂层将散热器附接到模具，并且在它们之间提供热路径。 此外，散热器从塑料体突出，并且具有尺寸和形状的端部，以与相邻封装上的散热器互锁以形成电子组件。 在电子组件中，互锁散热器保持物理接触的散热器上的接触表面并改善封装的散热。 替代实施例包装包括附接一对散热器并封装管芯的导热密封剂。

公开(公告)号：US20010008302A1

公开(公告)日：2001-07-19

申请号：US09771617

申请日：2001-01-30

Inventor： Gen Murakami ,  Kunihiro Tsubosaki ,  Masahiro Ichitani ,  Kunihiko Nishi ,  Ichiro Anjo ,  Asao Nishimura ,  Makoto Kitano ,  Akihiro Yaguchi ,  Sueo Kawai ,  Masatsugu Ogata ,  Syuuji Eguchi ,  Hiroyoshi Kokaku ,  Masanori Segawa ,  Hiroshi Hozoji ,  Takashi Yokoyama ,  Noriyuki Kinjo ,  Aizo Kaneda ,  Junichi Saeki ,  Shozo Nakamura ,  Akio Hasebe ,  Hiroshi Kikuchi ,  Isamu Yoshida ,  Takashi Yamazaki ,  Kazuyoshi Oshima ,  Tetsurou Matsumoto

IPC: H01L023/495

CPC classification number: H01L23/3107 ,  H01L23/4951 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49568 ,  H01L23/49586 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16245 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/4569 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/48799 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2224/92147 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/01043 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01092 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/144 ,  H05K1/181 ,  H05K3/3421 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/0695 ,  H01L2224/85399

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the nullLead-On-Chipnull or nullChip-On-Leadnull structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.