公开(公告)号：US6107123A

公开(公告)日：2000-08-22

申请号：US188599

申请日：1998-11-09

Applicant: Thomas H. Distefano ,  Joseph Fjelstad

Inventor： Thomas H. Distefano ,  Joseph Fjelstad

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L21/44

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49572 ,  H01L24/32 ,  H01L24/80 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/80203 ,  H01L2224/80207 ,  H01L2224/81192 ,  H01L2224/81904 ,  H01L2224/83209 ,  H01L2224/9212 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311

Abstract: A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component enapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer is created.

Abstract translation: 在未固化或部分固化的微电子元件助剂和粘合剂/芯片附着层中去除空隙和气泡的方法。 通过施加均匀的压力（等静压或静水压）和能量使得产生基本上无空隙/无气泡的中间层，基本上消除了微电子部件和支撑基板之间的间隙内的密封空隙或气泡。

公开(公告)号：US6093584A

公开(公告)日：2000-07-25

申请号：US85352

申请日：1998-05-27

Applicant: Joseph Fjelstad

Inventor： Joseph Fjelstad

IPC: D21F1/06 ,  D21G9/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L25/18 ,  H01L21/44

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/49 ,  H01L24/97 ,  H01L25/18 ,  H01L2221/68377 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/3011

Abstract: A method of manufacturing a semiconductor chip package. A sacrificial layer is used as a base to selectively form an array of conductive pads such that a central region is defined by the pads. A back surface of a semiconductor chip is next attached to the sacrificial layer within the central region between the pads so that the contact bearing surface of the chip faces away from the sacrificial layer. The chip contacts are then electrically connected to respective pads, typically by wire bonding a wire therebetween. A curable, dielectric liquid encapsulant is then deposited on the sacrificial layer such that the pads, electrical connections and chip are fully encapsulated, as by an overmolding operation. The encapsulant is then cured and the sacrificial layer is either completely removed or is selectively removed to expose a surface of the pads for electrical attachment to a PWB and the back surface of the chip for creating a direct thermal path from the chip to the PWB.

Abstract translation: 一种制造半导体芯片封装的方法。 牺牲层用作基底以选择性地形成导电焊盘的阵列，使得中心区域由焊盘限定。 接下来，半导体芯片的背面附着在焊盘之间的中心区域内的牺牲层，使得芯片的接触支承表面背离牺牲层。 芯片触点然后电连接到相应的焊盘，通常通过在其间引线接合线。 然后将可固化的介电液体密封剂沉积在牺牲层上，使得焊盘，电连接和芯片被完全封装，如通过包覆成型操作。 然后将密封剂固化并且牺牲层被完全去除或者被选择性地去除以暴露焊盘的表面以电连接到PWB和芯片的后表面，以形成从芯片到PWB的直接热路径。

公开(公告)号：US6002168A

公开(公告)日：1999-12-14

申请号：US978082

申请日：1997-11-25

Applicant: Pieter H. Bellaar ,  Thomas H. DiStefano ,  Joseph Fjelstad ,  Christopher M. Pickett ,  John W. Smith

Inventor： Pieter H. Bellaar ,  Thomas H. DiStefano ,  Joseph Fjelstad ,  Christopher M. Pickett ,  John W. Smith

IPC: H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  H05K3/40 ,  H01L23/48 ,  H01L23/06 ,  H01L23/52

CPC classification number: H01L23/49816 ,  H01L23/4985 ,  H05K3/3436 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H05K2201/049 ,  H05K2201/10234 ,  H05K2201/10378 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K3/284 ,  H05K3/4084 ,  Y02P70/613

Abstract: A microelectronic component for mounting a rigid substrate, such as a hybrid circuit to a rigid support substrate, such as a printed circuit board. The microelectronic component includes a rigid interposer which may have a chip mounted on its first surface; a pattern of contacts on the rigid interposer; a flexible interposer overlying the second surface of the rigid interposer; a pattern of terminals on the flexible interposer; flexible leads; and solder coated copper balls mounted on the flexible interposer. The microelectronic component may have a socket assembly mounted on the first surface of the rigid interposer. The microelectronic component may be mounted on a rigid support substrate.

Abstract translation: 一种微电子部件，用于将诸如混合电路的刚性基板安装到刚性支撑基板，例如印刷电路板。 微电子部件包括可以在其第一表面上安装芯片的刚性插入器; 刚性插入件上的接触图案; 位于刚性插入件的第二表面上的柔性插入件; 柔性插入器上的端子图案; 柔性线 以及安装在柔性插入件上的焊接铜球。 微电子部件可以具有安装在刚性插入件的第一表面上的插座组件。 微电子部件可以安装在刚性支撑基板上。

公开(公告)号：US5821609A

公开(公告)日：1998-10-13

申请号：US807470

申请日：1997-02-27

Applicant: Thomas H. DiStefano ,  John W. Smith ,  Konstantine Karavakis ,  Joseph Fjelstad

Inventor： Thomas H. DiStefano ,  John W. Smith ,  Konstantine Karavakis ,  Joseph Fjelstad

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L24/86 ,  H01L21/4846 ,  H01L23/4985 ,  H01L23/49861 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  Y10T29/49121

Abstract: A semiconductor chip connection component having numerous leads extending side-by-side across a gap in a support structure, each lead having a frangible section to permit detachment of one end of the lead from the support structure in a bonding process. The frangible sections are formed by treating the lead-forming material in an elongated treatment zone extending across the regions occupied by numerous leads. The process avoids the need for especially fine etching to form notches in the lateral edges of the leads.

Abstract translation: 一种半导体芯片连接部件，其具有多个引线，跨越支撑结构中的间隙并排延伸，每个引线具有易碎部分，以允许引线的一端在接合过程中从支撑结构脱离。 通过在延伸的处理区域中处理引线形成材料形成脆性部分，该处理区域延伸穿过由许多引线占据的区域。 该工艺避免了在引线的侧边缘上特别细蚀刻形成凹口的需要。

公开(公告)号：US5821608A

公开(公告)日：1998-10-13

申请号：US709127

申请日：1996-09-06

Applicant: Thomas H. DiStefano ,  Joseph Fjelstad ,  John W. Smith

Inventor： Thomas H. DiStefano ,  Joseph Fjelstad ,  John W. Smith

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L23/02

CPC classification number: H01L24/48 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/05599 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A semiconductor chip package includes a substrate having a first surface and a second surface and a gap extending from the first surface to the second surface. The substrate defines a plane which is substantially parallel to the first and second surfaces. The substrate has conductive terminals accessible and the second surface and bond pads. Conductive leads extend across the gap whereby each lead electrically interconnects one of the conductive terminals and one of the bond pads. Each lead includes an expansion section within the gap which is laterally curved with respect to the plane. A semiconductor chip having a back surface and a face surface is assembled to the substrate. The face surface includes a plurality of contacts on the periphery of the face surface of the chip whereby the chip contracts are electrically connected to the bond pads on the substrate.

Abstract translation: 半导体芯片封装包括具有第一表面和第二表面的衬底以及从第一表面延伸到第二表面的间隙。 衬底限定基本上平行于第一表面和第二表面的平面。 衬底具有可接触的导电端子和第二表面和接合焊盘。 导电引线延伸穿过间隙，由此每个引线将导电端子中的一个导电互连，并且其中一个接合焊盘。 每个引线包括在间隙内的相对于平面横向弯曲的膨胀部分。 将具有背面和表面的半导体芯片组装到基板上。 面表面包括在芯片的表面的周边上的多个触点，由此芯片收缩电连接到衬底上的接合焊盘。

公开(公告)号：US20110095441A1

公开(公告)日：2011-04-28

申请号：US12974744

申请日：2010-12-21

Applicant: Joseph Fjelstad ,  Konstantine Karavakis

Inventor： Joseph Fjelstad ,  Konstantine Karavakis

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/498 ,  H01L23/525 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/72 ,  H01L24/82 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2224/11334 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16 ,  H01L2224/24011 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/274 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/85424 ,  H01L2924/00011 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/01004

Abstract: A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract translation: 兼容的半导体芯片封装组件包括具有多个芯片触点的半导体芯片和具有顶表面，底表面和倾斜周边边缘的柔性层，由此柔性层的底表面覆盖在半导体芯片的表面上。 组件还包括连接到半导体芯片的芯片触点的多个导电迹线，迹线沿倾斜边缘延伸到柔性层的顶表面。 组件可以包括覆盖半导体芯片的导电端子，其中柔性层将导电端子支撑在半导体芯片上。 导电迹线具有与半导体芯片的触点电连接的第一端和与导电端子电连接的第二端。 导电端子可相对于半导体芯片移动。

公开(公告)号：US20070236901A1

公开(公告)日：2007-10-11

申请号：US11748045

申请日：2007-05-14

Applicant: Kevin Grundy ,  Gary Yasumura ,  Joseph Fjelstad ,  William Wiedemann ,  Para Segaram

Inventor： Kevin Grundy ,  Gary Yasumura ,  Joseph Fjelstad ,  William Wiedemann ,  Para Segaram

IPC: H01R12/16

CPC classification number: H01R12/52 ,  H01R12/7011 ,  H01R12/7082 ,  H01R12/714 ,  H01R12/716 ,  H01R12/721 ,  H01R13/24 ,  H01R31/06 ,  H05K1/0237 ,  H05K1/14 ,  H05K1/147 ,  H05K3/222 ,  H05K7/1441 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: A signal-segregating connector for use in a system having a printed circuit board, a first electrical structure and a second electrical structure. The connector includes a first set of conductive elements to convey signals between the first electrical structure and the printed circuit board, and a second set of conductive elements to convey signals between the first electrical structure and the second electrical structure.

Abstract translation: 一种用于具有印刷电路板，第一电气结构和第二电气结构的系统中的信号分离连接器。 连接器包括用于在第一电气结构和印刷电路板之间传送信号的第一组导电元件和用于在第一电结构和第二电结构之间传送信号的第二组导电元件。

公开(公告)号：US20070178774A1

公开(公告)日：2007-08-02

申请号：US11607143

申请日：2006-12-01

Applicant: Gary Yasumura ,  Joseph Fjelstad ,  Kevin Grundy ,  William Wiedemann ,  Matthew Stepovich

Inventor： Gary Yasumura ,  Joseph Fjelstad ,  Kevin Grundy ,  William Wiedemann ,  Matthew Stepovich

IPC: H01R4/48

CPC classification number: H05K3/326 ,  H01R12/714 ,  H01R12/79 ,  H01R13/2407 ,  H01R13/658 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/0979

Abstract: An electrical interconnection device for establishing redundant contacts between the ends of two conductive elements to be mated, creating a electrical interconnection without capacitive stubs.

Abstract translation: 一种电互连装置，用于在要配合的两个导电元件的端部之间建立冗余触点，产生不具有电容短截线的电互连。

公开(公告)号：US07095054B2

公开(公告)日：2006-08-22

申请号：US10948898

申请日：2004-09-24

Applicant: Joseph Fjelstad

Inventor： Joseph Fjelstad

IPC: H01L31/12

CPC classification number: H01L21/568 ,  H01L21/4832 ,  H01L21/56 ,  H01L21/561 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L31/0203 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48475 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2224/85051 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A microelectronic package includes a light sensitive microelectronic element having a front face including one or more contacts and a rear surface, and conductive leads having first ends connected to the one or more contacts and second ends connected to one or more conductive pads adjacent the light sensitive microelectronic element. The package also includes an at least partially transparent encapsulant covering the light sensitive microelectronic element, the conductive leads and the one or more conductive pads, whereby the one or more conductive pads are exposed on a surface of the encapsulant.

Abstract translation: 微电子封装包括具有包括一个或多个触点和后表面的前表面的光敏微电子元件，以及导电引线，其具有连接到一个或多个触点的第一端和连接到与光敏感相邻的一个或多个导电焊盘的第二端 微电子元件。 封装还包括覆盖光敏微电子元件，导电引线和一个或多个导电焊盘的至少部分透明的密封剂，由此一个或多个导电焊盘暴露在密封剂的表面上。

公开(公告)号：US20060157846A1

公开(公告)日：2006-07-20

申请号：US11353564

申请日：2006-02-13

Applicant: Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Kevin Grundy ,  Inessa Obenhuber

Inventor： Joseph Fjelstad ,  Para Segaram ,  Thomas Obenhuber ,  Kevin Grundy ,  Inessa Obenhuber

IPC: H01L23/52

CPC classification number: H01L24/85 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49537 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/32245

Abstract: An IC package having multiple surfaces for interconnection with interconnection elements making connections from the IC chip to the I/O terminations of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.