公开(公告)号：US06194315B1

公开(公告)日：2001-02-27

申请号：US09293212

申请日：1999-04-16

申请人： Yongjun Jeff Hu ,  Li Li

发明人： Yongjun Jeff Hu ,  Li Li

IPC分类号： H01L2144

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868

摘要： A liner material and method of use is disclosed. The method includes depositing a silicon layer into a deep void, such as a via or trench, and physical vapor depositing a cobalt seed layer onto the silicon. A supplemental cobalt layer is electroplated over the seed layer. The structure is then annealed, forming cobalt silicide (CoSix). The layer can be made very thin, facilitating further filling the via with highly conductive metals. Advantageously, the layer is devoid of oxygen and nitrogen, and thus allows low temperature metal reflows in filling the via. The liner material has particular utility in a variety of integrated circuit metallization processes, such as damascene and dual damascene processes.

公开(公告)号：US12051621B2

公开(公告)日：2024-07-30

申请号：US17825405

申请日：2022-05-26

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

IPC分类号： H01L21/768 ,  B24B37/04 ,  B81B7/00 ,  B81C1/00 ,  C23F3/00 ,  H01L21/306 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/00 ,  C23F1/18 ,  H01L23/522 ,  H01L25/065

CPC分类号： H01L21/76868 ,  B24B37/042 ,  B81B7/0006 ,  B81C1/00095 ,  C23F3/00 ,  H01L21/30625 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76883 ,  H01L24/80 ,  H01L24/81 ,  C23F1/18 ,  H01L21/76898 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/80031 ,  H01L2224/80895 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/1433 ,  H01L2924/00012 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014

摘要： Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

公开(公告)号：US11923197B2

公开(公告)日：2024-03-05

申请号：US17660532

申请日：2022-04-25

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu

IPC分类号： H01L21/027 ,  B81C1/00 ,  B82Y40/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/768

CPC分类号： H01L21/0271 ,  B81C1/00031 ,  B82Y40/00 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76868 ,  B81C2201/0149 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.

公开(公告)号：US10079210B2

公开(公告)日：2018-09-18

申请号：US15186825

申请日：2016-06-20

申请人： Samsung Electronics Co., Ltd.

发明人： Do-sun Lee ,  Do-hyun Lee ,  Chul-sung Kim ,  Sang-jin Hyun ,  Joon-gon Lee

IPC分类号： H01L21/02 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76876 ,  H01L23/485 ,  H01L23/53209 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/785

摘要： An integrated circuit device including a substrate having at least one fin-shaped active region, the at least one fin-shaped active region extending in a first direction, a gate line extending on the at least one fin-shaped active region in a second direction, the second direction intersecting with the first direction, a conductive region on a portion of the at least one fin-shaped active region at one side of the gate line, and a contact plug extending from the conductive region in a third direction, the third direction being perpendicular to a main plane of the substrate, may be provided. The contact plug may include a metal plug, a conductive barrier film on the conductive region, the conductive barrier film surrounding a sidewall and a bottom surface of the metal plug, the conductive barrier film including an N-rich metal nitride film, and a metal silicide film between the conductive region and the conductive barrier film.

公开(公告)号：US09922836B2

公开(公告)日：2018-03-20

申请号：US15320183

申请日：2014-08-28

申请人： Mitsubishi Electric Corporation

发明人： Koichiro Nishizawa ,  Akira Kiyoi

IPC分类号： H01L21/44 ,  H01L21/288 ,  H01L21/768

CPC分类号： H01L21/288 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76868 ,  H01L21/76874 ,  H01L21/76883

摘要： A semiconductor device manufacturing method of present application includes a catalytic step of depositing catalytic metal on a surface of a semiconductor substrate, an oxide removing step of removing oxide formed on the surface of the semiconductor substrate in the catalytic step, an additional catalytic step of depositing catalytic metal on the surface of the semiconductor substrate exposed in the oxide removing step, and a plating step of forming a metal film on the surface of the semiconductor substrate by means of an electroless plating method after the additional catalytic step.

公开(公告)号：US09911609B2

公开(公告)日：2018-03-06

申请号：US15606601

申请日：2017-05-26

申请人： Micron Technology, Inc.

发明人： Gurtej S. Sandhu

IPC分类号： H01L51/40 ,  G01N15/06 ,  G01N33/00 ,  G01N33/48 ,  H01L21/033 ,  H01L21/308 ,  B81C1/00 ,  H01L21/768

CPC分类号： H01L21/0338 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/76868 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a nanostructure comprises forming self-assembled nucleic acids on at least a portion of a substrate. The method further comprises contacting the self-assembled nucleic acids on the at least a portion of a substrate with a solution comprising at least one repair enzyme to repair defects in the self-assembled nucleic acids. The method may comprise repeating the repair of defects in the self-assembled nucleic acids on the at least a portion of a substrate until a desired, reduced threshold level of defect density is achieved. A semiconductor structure comprises a pattern of self-assembled nucleic acids defining a template having at least one aperture therethrough. At least one of the apertures has a dimension of less than about 50 nm.

公开(公告)号：US20180019214A1

公开(公告)日：2018-01-18

申请号：US15657666

申请日：2017-07-24

申请人： GLOBALFOUNDRIES INC.

发明人： Ronald G. FILIPPI ,  Erdem KALTALIOGLU ,  Andrew T. KIM ,  Ping-Chuan WANG

IPC分类号： H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L23/562 ,  H01L21/76868 ,  H01L21/76898 ,  H01L23/481

摘要： Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially through a backside of a thinned wafer attached to a carrier wafer. The method further includes depositing material within the trenches or vias to form reinforcement structures on the backside of the thinned wafer. The method further includes removing excess material from a surface of the thinned wafer, which was deposited during the depositing of the material within the vias.

公开(公告)号：US09576867B2

公开(公告)日：2017-02-21

申请号：US15093528

申请日：2016-04-07

申请人： Infineon Technologies AG

发明人： Georg Meyer-Berg ,  Reinhard Pufall

IPC分类号： H01L23/48 ,  H01L21/66 ,  G01R31/26 ,  G01R31/28 ,  H01L23/58 ,  H01L21/768 ,  H01L23/532 ,  H01L23/00 ,  H01L23/522 ,  H01L23/525

CPC分类号： H01L22/32 ,  G01R31/26 ,  G01R31/28 ,  G01R31/2853 ,  G01R31/2884 ,  H01L21/7685 ,  H01L21/76868 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/525 ,  H01L23/53204 ,  H01L23/58 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/05556 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

摘要： Device comprising a ductile layer, a method for making a component comprising a ductile layer and a method for testing a component are disclosed. An embodiment includes an electronic device including a first conductive layer, a ductile layer and a brittle layer between the first conductive layer and the ductile layer.

摘要翻译： 公开了包括延展层的装置，用于制造包括延展层的部件的方法和用于测试部件的方法。 实施例包括在第一导电层和延性层之间包括第一导电层，延性层和脆性层的电子器件。

公开(公告)号：US09514928B2

公开(公告)日：2016-12-06

申请号：US14155884

申请日：2014-01-15

申请人： Taiwan Semiconductor Manufacturing CO., LTD.

发明人： Chih-Chien Chi ,  Chung-Chi Ko ,  Mei-Ling Chen ,  Huang-Yi Huang ,  Szu-Ping Tung ,  Ching-Hua Hsieh

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/02107 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76868 ,  Y10T428/24331

摘要： A selectively repairing process for a barrier layer is provided. A repair layer is formed by chemical vapor deposition using an organosilicon compound as a precursor gas. The precursor gas adsorbed on a low-k dielectric layer exposed by defects in a barrier layer is transformed to a porous silicon oxide layer has a density more than the density of the low-k dielectric layer.

摘要翻译： 提供了一种用于阻挡层的选择性修复方法。 使用有机硅化合物作为前体气体通过化学气相沉积形成修复层。 吸附在由阻挡层中的缺陷暴露的低k电介质层上的前体气体转变为具有比低k电介质层的密度更高的密度的多孔氧化硅层。

公开(公告)号：US09234293B2

公开(公告)日：2016-01-12

申请号：US14507692

申请日：2014-10-06

申请人： APPLIED Materials, Inc.

发明人： Rajesh Baskaran ,  Robert W. Batz, Jr. ,  Bioh Kim ,  Thomas L. Ritzdorf ,  John Lee Klocke ,  Kyle M. Hanson

IPC分类号： C25D17/00 ,  C25D7/12 ,  C25D5/02 ,  C25D3/38 ,  C25F3/02 ,  H01L21/288 ,  H01L21/768 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/34 ,  C25D3/46 ,  C25D3/54 ,  C25D21/12 ,  H05K3/42

CPC分类号： C25D5/028 ,  C25D3/12 ,  C25D3/20 ,  C25D3/30 ,  C25D3/34 ,  C25D3/38 ,  C25D3/46 ,  C25D3/54 ,  C25D5/022 ,  C25D17/001 ,  C25D17/002 ,  C25D21/12 ,  C25F3/02 ,  H01L21/2885 ,  H01L21/76846 ,  H01L21/76868 ,  H01L21/76873 ,  H05K3/423

摘要： Processes and systems for electrolytically processing a microfeature workpiece with a first processing fluid and a counter electrode are described. Microfeature workpieces are electrolytically processed using a first processing fluid, a counter electrode, a second processing fluid, and an anion permeable barrier layer. The anion permeable barrier layer separates the first processing fluid from the second processing fluid while allowing certain anionic species to transfer between the two fluids.

摘要翻译： 描述了利用第一处理流体和对电极对微特征工件进行电解处理的工艺和系统。 使用第一处理流体，对电极，第二处理流体和阴离子可渗透阻挡层对微特征工件进行电解处理。 阴离子可渗透阻挡层将第一处理流体与第二处理流体分离，同时允许某些阴离子物质在两种流体之间转移。