公开(公告)号：US20060030073A1

公开(公告)日：2006-02-09

申请号：US11242557

申请日：2005-10-03

Applicant: W. Reeder ,  Tongbi Jiang

Inventor： W. Reeder ,  Tongbi Jiang

IPC: H01L21/50

CPC classification number: H01L24/83 ,  H01L21/67132 ,  H01L23/3737 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/75 ,  H01L25/50 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/351 ,  H01R4/04 ,  H05K3/0058 ,  H05K3/305 ,  H05K3/386 ,  H05K2203/0278 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for securing a semiconductor device component to another element is provided. An adhesive material includes a pressure-sensitive component and a curable component is used to at least temporarily secure the semiconductor device component and the other element to each other. The pressure-sensitive component of the adhesive material temporarily secures the semiconductor device component and the other element to one another. When the semiconductor device component and the other element are properly aligned, the curable component of the adhesive material may be cured to more permanently secure them to one another. For example, when a thermoset material is used as the curable component, it may be cured by heating, such as at a temperature of lower than about 200° C. and as low as about 120° C. or less.

Abstract translation: 提供了一种用于将半导体器件部件固定到另一元件的方法。 粘合剂材料包括压敏部件，并且可固化部件用于至少将半导体器件部件和另一个元件临时固定。 粘合剂材料的压敏部件将半导体器件部件和另一个元件彼此临时固定。 当半导体器件部件和另一个元件被正确地对准时，粘合剂材料的可固化部件可以被固化以使它们彼此更加永久地固定。 例如，当将热固性材料用作可固化组分时，其可以通过加热固化，例如在低于约200℃的温度和低至约120℃或更低的温度下固化。

公开(公告)号：US20050277279A1

公开(公告)日：2005-12-15

申请号：US10867023

申请日：2004-06-14

Applicant: Shijian Luo ,  Tongbi Jiang

Inventor： Shijian Luo ,  Tongbi Jiang

IPC: H01L21/28 ,  H01L21/44 ,  H01L21/56 ,  H01L23/485

CPC classification number: H01L24/10 ,  H01L21/561 ,  H01L21/563 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Microfeature devices, microfeature workpieces, and methods for manufacturing microfeature devices and microfeature workpieces are disclosed herein. The microfeature workpieces have an integrated circuit, a surface, and a plurality of interconnect elements projecting from the surface and arranged in arrays on the surface. In one embodiment, a method includes forming a coating on the interconnect elements of the microfeature workpiece, producing a layer over the surface of the microfeature workpiece after forming the coating, and removing the coating from at least a portion of the individual interconnect elements. The coating has a surface tension less than a surface tension of the interconnect elements to reduce the extent to which the material in the layer wicks up the interconnect elements and produces a fillet at the base of the individual interconnect elements.

Abstract translation: 本文公开了微特征装置，微特征工件以及用于制造微特征装置和微特征工件的方法。 微型工件具有集成电路，表面和从表面突出并且在表面上排列成阵列的多个互连元件。 在一个实施例中，一种方法包括在微特征工件的互连元件上形成涂层，在形成涂层之后在微特征工件的表面上产生一层，以及从单个互连元件的至少一部分去除涂层。 涂层具有小于互连元件的表面张力的表面张力，以减少层中的材料吸收互连元件的程度，并在单个互连元件的基部产生圆角。

公开(公告)号：US06972200B2

公开(公告)日：2005-12-06

申请号：US10693286

申请日：2003-10-23

Applicant: Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

Inventor： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

IPC: G01R1/04 ,  H01L21/66

CPC classification number: G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Abstract translation: 每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。 在通过将集成电路（IC）芯片压在基板上的互连凸块以进行电连接的环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附着的那些组件，而使用“干”环氧树脂 可以在测试之前治愈。 在任一情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且在修理期间需要使用“已知的好的骰子”（KGD）返工程序。

公开(公告)号：US06967113B2

公开(公告)日：2005-11-22

申请号：US10721110

申请日：2003-11-24

Applicant: Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

Inventor： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

IPC: G01R1/04 ,  G01R31/26

CPC classification number: G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

公开(公告)号：US06949834B2

公开(公告)日：2005-09-27

申请号：US10793234

申请日：2004-03-04

Applicant: Mike Connell ,  Tongbi Jiang

Inventor： Mike Connell ,  Tongbi Jiang

IPC: H01L21/56 ,  H01L21/60 ,  H01L23/31 ,  H01L23/495 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L24/48 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/4951 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/49 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05073 ,  H01L2224/05111 ,  H01L2224/05118 ,  H01L2224/05155 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/274 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/451 ,  H01L2224/45111 ,  H01L2224/45118 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48666 ,  H01L2224/48669 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48766 ,  H01L2224/48769 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/48866 ,  H01L2224/4943 ,  H01L2224/73215 ,  H01L2224/83101 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/85444 ,  H01L2224/92 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06558 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10161 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/07025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/48824 ,  H01L2224/48869 ,  H01L2224/48744 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/20754 ,  H01L2224/45099 ,  H01L2224/4554

Abstract: A semiconductor package includes a substrate, a die attached and wire bonded to the substrate, and a die encapsulant encapsulating the die. The die includes a circuit side having a pattern of die contacts, planarized wire bonding contacts bonded to the die contacts, and a planarized polymer layer on the circuit side configured as stress defect barrier. A method for fabricating the package includes the steps of forming bumps on the die, encapsulating the bumps in a polymer layer, and then planarizing the polymer layer and the bumps to form the planarized wire bonding contacts. The method also includes the steps of attaching and wire bonding the die to the substrate, and then forming the die encapsulant on the die.

Abstract translation: 半导体封装包括衬底，附接的芯片和引线键合到衬底，以及封装模具的管芯密封剂。 芯片包括具有芯片触点图案的电路侧，与芯片触点接合的平坦化引线接合触点，以及被配置为应力缺陷屏障的电路侧上的平坦化聚合物层。 制造封装的方法包括以下步骤：在芯片上形成凸块，将凸块封装在聚合物层中，然后平坦化聚合物层和凸块以形成平坦化的引线接合触点。 该方法还包括以下步骤：将管芯附着和引线接合到衬底，然后在管芯上形成管芯密封剂。

公开(公告)号：US06906417B2

公开(公告)日：2005-06-14

申请号：US10011686

申请日：2001-11-13

Applicant: Tongbi Jiang ,  Salman Akram

Inventor： Tongbi Jiang ,  Salman Akram

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L23/48 ,  B23K31/02

CPC classification number: H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/3436 ,  H05K2201/0212 ,  H05K2201/10234 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05611 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655

Abstract: A ball grid array for a flip-chip assembly. The ball grid array includes a plurality of bumps bonded between an active surface of a semiconductor die and a top surface of a printed circuit board or any type of substrate carrier. The plurality of balls include at least one bump having a core material and an outer layer. The rigidity of the core material is greater than that of the material of the outer layer. Additionally, the melting temperature of the core material is higher than the material of the outer layer. By this arrangement, the core material with an outer layer provides bumps that are substantially uniform in height. In addition, the balls only procure marks or deformation to the core material during burn-in testing and reflow.

Abstract translation: 用于倒装芯片组合的球栅阵列。 球栅阵列包括结合在半导体管芯的有源表面和印刷电路板的顶表面之间的多个凸起或任何类型的衬底载体。 多个球包括至少一个具有芯材料和外层的凸块。 芯材的刚性大于外层材料的刚性。 此外，芯材料的熔化温度高于外层的材料。 通过这种布置，具有外层的芯材料提供高度基本均匀的凸块。 此外，在老化测试和回流过程中，球只会对芯材料产生痕迹或变形。

公开(公告)号：US06902956B2

公开(公告)日：2005-06-07

申请号：US10041322

申请日：2002-01-07

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L23/12 ,  H01L21/44 ,  H01L21/58 ,  H01L21/60 ,  H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/053

CPC classification number: H01L24/16 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16237 ,  H01L2224/29013 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/30131 ,  H01L2224/32014 ,  H01L2224/48 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81903 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01045 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/45099

Abstract: A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.

Abstract translation: 一种用于球栅阵列型封装的半导体封装结构，其使用多个粘合弹性体膜将半导体管芯附着到具有导电迹线的衬底，以便减轻半导体管芯和印刷电路板之间的热失配应力， 封装的器件被焊接，同时保持封装器件本身的可靠性。

公开(公告)号：US06894380B2

公开(公告)日：2005-05-17

申请号：US10230005

申请日：2002-08-28

Applicant: Tongbi Jiang ,  Michael E. Connell

Inventor： Tongbi Jiang ,  Michael E. Connell

IPC: H01L21/58 ,  H01L21/68 ,  H01L21/78 ,  H01L21/98 ,  H01L25/065 ,  H01L23/02

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A method of packaging semiconductor devices is described. In one embodiment, the method comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto. In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area.

Abstract translation: 描述了一种封装半导体器件的方法。 在一个实施例中，该方法包括提供晶片安装带的一部分，向晶片安装带施加粘合剂层，拉伸晶片安装带和粘合剂层，将晶片连接到拉伸的粘合剂层，切割晶片和粘合剂 将晶片切割成多个模具，并固化晶片安装带。 在另外的实施例中，该方法包括从晶片安装带去除多个管芯中的至少一个，所述移除的管芯具有与其连接的粘合层的一部分，提供具有多个与其连接的引线接合的管芯， 将去除的芯片上的粘合剂层连接到具有与其结合的引线键合的管芯。 在另一方面，本发明涉及多个层叠的半导体器件，其包括第一裸片，第一裸片具有上表面，第二裸片位于第一裸片上，第二片具有底表面，以及粘合剂 层，其定位在第一模具和第二模具中的每一个之间并且耦合到第一模具和第二模具中，粘合剂层由第一和第二表面组成，粘合剂层的第一表面耦合到第二模具的底表面，从而限定第一接触区域， 粘合剂层的第二表面耦合到第一模具的上表面，从而限定第二接触区域，第二接触区域小于第一接触区域。

公开(公告)号：US20050040533A1

公开(公告)日：2005-02-24

申请号：US10932835

申请日：2004-09-01

Applicant: Warren Farnworth ,  Tongbi Jiang

Inventor： Warren Farnworth ,  Tongbi Jiang

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/02203 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/02345 ,  H01L21/02354 ,  H01L21/31695 ,  H01L21/7682 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Semiconductor devices with porous insulative materials are disclosed. The porous insulative materials may include a consolidated material with voids dispersed therethrough. The voids may be defined by shells of microcapsules. The voids impart the dielectric materials with reduced dielectric constants and, thus, increased electrical insulation properties.

Abstract translation: 公开了具有多孔绝缘材料的半导体器件。 多孔绝缘材料可以包括具有分散在其中的空隙的固结材料。 空隙可以由微胶囊的壳定义。 空隙赋予介电材料具有降低的介电常数，从而提高电绝缘性能。

公开(公告)号：US06858927B2

公开(公告)日：2005-02-22

申请号：US09971952

申请日：2001-10-04

Applicant: Casey Prindiville ,  Tongbi Jiang ,  Bret Street

Inventor： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

IPC: H01L21/56 ,  H01L21/66 ,  H01L23/48

CPC classification number: H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

Abstract: Semiconductor package support elements including cover members attached to one or more reject die sites are provided. Methods for making the support elements of the present invention and for making semiconductor packages using the same are also provided. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

Abstract translation: 提供了包括附接到一个或多个废弃模具位置的盖构件的半导体封装支撑元件。 还提供了制造本发明的支撑元件和制造使用其的半导体封装件的方法。 在使用盖构件的封装工艺之前，覆盖支撑元件的有缺陷的基底上的模具位置。 盖构件包括例如压敏或温度活化的带，废模或类似物。 本发明的支撑元件和方法由于存在废弃模具位置而实际上消除了在封装期间的渗出或闪烁。 本发明的支撑元件和方法进一步确保功能性骰子不会被附着到废弃模具位置而牺牲，从而降低制造成本，同时提高功能性半导体封装的产量。