公开(公告)号：US20160284661A1

公开(公告)日：2016-09-29

申请号：US15181740

申请日：2016-06-14

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Matthias Stecher

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/48 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00 ,  H01L2924/013 ,  H01L2924/2075 ,  H01L2924/00012 ,  H01L2924/01006

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

公开(公告)号：US08993381B2

公开(公告)日：2015-03-31

申请号：US14244933

申请日：2014-04-04

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L21/561 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/495 ,  H01L23/4951 ,  H01L24/06 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/13 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/27464 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/30181 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83801 ,  H01L2224/83805 ,  H01L2224/8381 ,  H01L2224/8382 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929

Abstract: A method for forming a thin semiconductor device is disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection.

Abstract translation: 公开了一种用于形成薄半导体器件的方法。 在一个实施例中，引线框架设置在载体上。 至少一个半导体芯片设置在引线框架上，并且至少一个半导体芯片被封装材料包围。 至少一个半导体芯片和封装材料的厚度减小。 在封装材料中形成至少一个贯通连接，并且至少一个电接触元件形成在至少一个半导体芯片和至少一个贯穿连接上。

公开(公告)号：US20140138843A1

公开(公告)日：2014-05-22

申请号：US13681079

申请日：2012-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Georg Meyer-Berg ,  Khalil Hosseini ,  Joachim Mahler ,  Edward Fuergut

IPC: H01L23/538 ,  H01L21/58 ,  H01L21/78

CPC classification number: H01L23/5384 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/49513 ,  H01L23/49562 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83203 ,  H01L2224/83207 ,  H01L2224/83439 ,  H01L2224/83455 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/00

Abstract: A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier.

Abstract translation: 提供载体和半导体芯片。 连接层被施加到半导体芯片的第一主面。 连接层包括多个凹陷。 将填料施加到连接层或载体上。 将半导体芯片附着到载体上，使得连接层设置在半导体芯片和载体之间。 半导体芯片固定在载体上。

公开(公告)号：US20140138841A1

公开(公告)日：2014-05-22

申请号：US13678675

申请日：2012-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H01L23/48 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3171 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side.

Abstract translation: 提供一种集成电路，所述集成电路包括：具有第一芯片侧和与所述第一芯片侧相对的第二芯片侧的芯片，所述芯片在所述第二芯片侧具有至少一个接触区域; 封装材料至少部分覆盖芯片; 以及至少一个接触通孔，其包括与所述至少一个接触区域接触并延伸穿过所述封装材料并通过所述芯片在所述第一芯片侧和所述第二芯片侧之间的导电材料。

公开(公告)号：US20190103378A1

公开(公告)日：2019-04-04

申请号：US16148316

申请日：2018-10-01

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Khalil Hosseini ,  Johannes Lodermeyer ,  Joachim Mahler ,  Thorsten Meyer ,  Georg Meyer-Berg ,  Ivan Nikitin ,  Reinhard Pufall ,  Edmund Riedl ,  Klaus Schmidt ,  Manfred Schneegans ,  Patrick Schwarz

IPC: H01L23/00

Abstract: A metallic interconnection and a semiconductor arrangement including the same are described, wherein a method of manufacturing the same may include: providing a first structure including a first metallic layer having protruding first microstructures; providing a second structure including a second metallic layer having protruding second microstructures; contacting the first and second microstructures to form a mechanical connection between the structures, the mechanical connection being configured to allow fluid penetration; removing one or more non-metallic compounds on the first metallic layer and the second metallic layer with a reducing agent that penetrates the mechanical connection and reacts with the one or more non-metallic compounds; and heating the first metallic layer and the second metallic layer at a temperature causing interdiffusion of the first metallic layer and the second metallic layer to form the metallic interconnection between the structures.

公开(公告)号：US09559078B2

公开(公告)日：2017-01-31

申请号：US14581653

申请日：2014-12-23

Applicant: Infineon Technologies AG

Inventor： Joachim Mahler ,  Manfred Mengel ,  Khalil Hosseini ,  Klaus Schmidt ,  Franz-Peter Kalz

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L24/00 ,  H01L24/24 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L2224/04026 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/245 ,  H01L2224/2499 ,  H01L2224/26165 ,  H01L2224/27462 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/82002 ,  H01L2224/82101 ,  H01L2224/82345 ,  H01L2224/82385 ,  H01L2224/82986 ,  H01L2224/831 ,  H01L2224/83851 ,  H01L2224/92144 ,  H01L2924/01327 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01047

Abstract: An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap.

Abstract translation: 电子部件包括导电载体。 导电载体包括载体表面，半导体芯片包括芯片表面。 载体表面和芯片表面中的一个或两个包括非平面结构。 芯片附着到载体上，其芯片表面面向载体表面，使得由于载体表面和第一芯片表面之一或两者的非平面结构，在芯片表面和载体表面之间提供间隙 。 电子部件还包括位于间隙中的第一电沉积金属层。

公开(公告)号：US09530754B2

公开(公告)日：2016-12-27

申请号：US14880373

申请日：2015-10-12

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Franz-Peter Kalz ,  Joachim Voelter ,  Ralf Wombacher

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/48 ,  H01L21/50 ,  H01L21/56 ,  H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L23/492 ,  H01L23/498 ,  H01L23/31

CPC classification number: H01L25/0655 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/492 ,  H01L23/49558 ,  H01L23/49575 ,  H01L23/49586 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/19 ,  H01L24/20 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83095 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/82 ,  H01L2224/83

Abstract: A chip package is provided. The chip package may include an electrically conductive carrier; at least one first chip including a first side and a second side opposite of the first side, with its second side being electrically contacted to the electrically conductive carrier; an insulating layer over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip; at least one second chip arranged over the insulating layer and next to the first chip; encapsulating material over the first chip and the second chip; and electrical contacts which extend through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip.

Abstract translation: 提供芯片封装。 芯片封装可以包括导电载体; 至少一个第一芯片，包括第一侧和与第一侧相对的第二侧，其第二侧与导电载体电接触; 在所述导电载体的至少一部分上方以及所述芯片的第一侧的至少一部分上的绝缘层; 至少一个第二芯片布置在所述绝缘层上并且靠近所述第一芯片; 封装材料在第一芯片和第二芯片上; 以及电触头，其通过封装材料延伸到至少一个第一芯片的至少一个触点和至少一个第二芯片的至少一个触点。

公开(公告)号：US09385107B2

公开(公告)日：2016-07-05

申请号：US13959712

申请日：2013-08-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/367 ,  H01L23/373 ,  H01L23/495 ,  H01L23/498 ,  H01L25/065 ,  H01L23/31 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L25/074 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49827 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/071 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/06181 ,  H01L2224/08168 ,  H01L2224/32225 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/3716 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/456 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material.

Abstract translation: 一种器件包括：衬底，其包括电绝缘芯，布置在衬底的第一主表面上的第一导电材料和布置在与第一主表面相对的衬底的第二主表面上的第二导电材料。 该装置还包括从第一主表面延伸到第二主表面并且电耦合第一导电材料和第二导电材料的导电连接，第一半导体芯片，布置在第一主表面上并电耦合到第一导电材料 导电材料和布置在第二主表面上并电耦合到第二导电材料的第二半导体芯片。

公开(公告)号：US09362193B2

公开(公告)日：2016-06-07

申请号：US13742456

申请日：2013-01-16

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Wolfram Hable ,  Manfred Mengel ,  Joachim Mahler ,  Khalil Hosseini

IPC: H01L23/373 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L23/06 ,  H01L23/495 ,  H01L23/00

Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.

公开(公告)号：US09249014B2

公开(公告)日：2016-02-02

申请号：US13670390

申请日：2012-11-06

Applicant: Infineon Technologies AG

Inventor： Khalil Hosseini ,  Joachim Mahler ,  Georg Meyer-Berg

IPC: H05K1/00 ,  B81C3/00 ,  C09J7/00 ,  H01L21/306 ,  H01L21/58 ,  H01L29/30 ,  H01L23/31 ,  H01L21/302 ,  H01L23/495 ,  H01L29/06 ,  H01L21/268 ,  H01L23/00 ,  H01L23/14 ,  B82Y30/00

CPC classification number: B81C3/00 ,  B82Y30/00 ,  C09J7/00 ,  C09J2201/602 ,  H01L21/268 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49513 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L29/30 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/03831 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05076 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05576 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29005 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29439 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83365 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15747 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  H01L2924/0665 ,  H01L2224/03 ,  H01L2924/206 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/05552

Abstract: An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier.

Abstract translation: 公开了组装组件和组件组装方法。 在一个实施例中，组装的部件包括部件载体，设置在部件载体上的附接层和设置在附着层上的部件，该部件具有面向部件载体的纳米结构的第一主表面。