公开(公告)号：US08399990B2

公开(公告)日：2013-03-19

申请号：US13355354

申请日：2012-01-20

Applicant: Yaojian Lin ,  Robert C. Frye

Inventor： Yaojian Lin ,  Robert C. Frye

IPC: H01L23/48

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer.

Abstract translation: 一种制造半导体器件的方法包括提供具有设置在基板的顶表面上的第一导电层的基板。 在基板和第一导电层上形成高电阻率层。 介电层沉积在衬底，第一导电层和高电阻率层上。 介电层，高电阻率层和第一导电层的一部分形成电容器叠层。 在电介质层上形成第一钝化层。 在电容器堆叠和第一钝化层的一部分上形成第二导电层。 在电介质层中蚀刻第一开口以暴露高电阻率层的表面。 在电介质层中的第一开口和第一钝化层的一部分上沉积第三和第四导电层。

公开(公告)号：US08395053B2

公开(公告)日：2013-03-12

申请号：US11769296

申请日：2007-06-27

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H01L21/4846 ,  H01L23/49548 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/04941 ,  H05K3/467 ,  H05K2201/0195 ,  H05K2201/0317 ,  H05K2201/09436 ,  H05K2201/09672 ,  Y10T29/43 ,  Y10T428/12528 ,  H01L2224/05599

Abstract: A circuit system comprising: forming a lower electrode over a substrate; forming a resistive film over the lower electrode; forming a multi-layered insulating stack over a portion of the resistive film; and forming an upper electrode over a portion of the multi-layered insulating stack.

Abstract translation: 一种电路系统，包括：在衬底上形成下电极; 在下电极上形成电阻膜; 在所述电阻膜的一部分上形成多层绝缘堆叠; 以及在所述多层绝缘堆叠的一部分上形成上电极。

公开(公告)号：US08309452B2

公开(公告)日：2012-11-13

申请号：US12826365

申请日：2010-06-29

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L21/44 ,  H01L21/60

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L28/10 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/056 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. A protective layer is formed over the passivation layer. The protective layer is removed over the first contact pad, but not from the second contact pad. A conductive layer is formed over the first contact pad. The conductive layer is coiled on the surface of the substrate to produce inductive properties. The formation of the conductive layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the protective layer. The protective layer is removed from the second contact pad after forming the conductive layer over the first contact pad. An external connection is formed on the second contact pad.

Abstract translation: 半导体器件具有在其表面上形成有电感器的基板。 第一和第二接触垫形成在基板上。 在衬底和第一和第二接触焊盘之上形成钝化层。 在钝化层上形成保护层。 保护层在第一接触垫上移除，但不从第二接触垫移除。 导电层形成在第一接触焊盘上。 导电层被卷绕在基板的表面上以产生电感性质。 导电层的形成涉及使用湿蚀刻剂。 第二接触垫被保护层从湿蚀刻剂保护。 在第一接触垫上形成导电层之后，从第二接触焊盘去除保护层。 在第二接触垫上形成外部连接。

公开(公告)号：US08304904B2

公开(公告)日：2012-11-06

申请号：US12700114

申请日：2010-02-04

Applicant: Yaojian Lin ,  Qing Zhang ,  Haijing Cao

Inventor： Yaojian Lin ,  Qing Zhang ,  Haijing Cao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11009 ,  H01L2224/11019 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2224/13099 ,  H01L2224/05552

Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the substrate and first conductive layer. A second conductive layer is formed over the first conductive layer and first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. The second insulating layer has a sidewall between a surface of the second insulating material and surface of the second conductive layer. A protective layer is formed over the second insulating layer and surface of the second conductive layer. The protective layer follows a contour of the surface and sidewall of the second insulating layer and second conductive layer. A bump is formed over the surface of the second conductive layer and a portion of the protective layer adjacent to the second insulating layer. The protective layer protects the second insulating layer.

Abstract translation: 半导体器件具有形成在衬底上的第一导电层。 第一绝缘层形成在衬底和第一导电层上。 在第一导电层和第一绝缘层上形成第二导电层。 在第一绝缘层和第二导电层上形成第二绝缘层。 第二绝缘层在第二绝缘材料的表面和第二导电层的表面之间具有侧壁。 在第二绝缘层和第二导电层的表面上形成保护层。 保护层遵循第二绝缘层和第二导电层的表面和侧壁的轮廓。 在第二导电层的表面上形成凸块，并且与第二绝缘层相邻的部分形成保护层。 保护层保护第二绝缘层。

公开(公告)号：US20120261817A1

公开(公告)日：2012-10-18

申请号：US13536120

申请日：2012-06-28

Applicant: Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

Inventor： Byung Tai Do ,  Stephen A. Murphy ,  Yaojian Lin ,  Heap Hoe Kuan ,  Pandi Chelvam Marimuthu ,  Hin Hwa Goh

IPC: H01L21/768 ,  H01L23/498

CPC classification number: H01L24/16 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05187 ,  H01L2224/05552 ,  H01L2224/05569 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2224/48811 ,  H01L2924/00 ,  H01L2224/48744 ,  H01L2924/00012

Abstract: A semiconductor wafer contains a plurality of semiconductor die. The wafer has contact pads formed over its surface. A passivation layer is formed over the wafer. A stress buffer layer is formed over the passivation layer. The stress buffer layer is patterned to expose the contact pads. A metal layer is deposited over the stress buffer layer. The metal layer is a common voltage bus for the semiconductor device in electrical contact with the contact pads. An adhesion layer, barrier layer, and seed layer is formed over the wafer in electrical contact with the contact pads. The metal layer is mounted to the seed layer. Solder bumps or other interconnect structures are formed over the metal layer. A second passivation layer is formed over the metal layer. In an alternate embodiment, a wirebondable layer can be deposited over the metal layer and wirebonds connected to the metal layer.

Abstract translation: 半导体晶片包含多个半导体管芯。 晶片具有在其表面上形成的接触垫。 在晶片上形成钝化层。 在钝化层上形成应力缓冲层。 将应力缓冲层图案化以暴露接触焊盘。 金属层沉积在应力缓冲层上。 金属层是用于与接触焊盘电接触的半导体器件的公共电压总线。 在与接触垫电接触的晶片之上形成粘合层，阻挡层和种子层。 金属层安装到种子层。 焊料凸块或其它互连结构形成在金属层上。 在金属层上形成第二钝化层。 在替代实施例中，可以将金属层沉积在金属层上，并且连接到金属层的引线键。

公开(公告)号：US08258612B2

公开(公告)日：2012-09-04

申请号：US12942084

申请日：2010-11-09

Applicant: Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Heap Hoe Kuan ,  Rui Huang ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L23/495

CPC classification number: H01L23/49861 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/495 ,  H01L23/49506 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method of manufacturing a semiconductor package system includes: forming a leadframe having a passive device; encapsulating the passive device to form an encapsulant interposer; attaching a first die to the encapsulant interposer; forming a substrate interposer having a second die; and stacking the encapsulant interposer over the substrate interposer.

Abstract translation: 制造半导体封装系统的方法包括：形成具有无源器件的引线框架; 封装无源器件以形成密封介质; 将第一管芯附接到所述密封剂插入件; 形成具有第二管芯的基板插入件; 并且将所述密封剂插入物堆叠在所述基板插入件上。

公开(公告)号：US20120211881A9

公开(公告)日：2012-08-23

申请号：US12763378

申请日：2010-04-20

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang

IPC: H01L23/538

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/013

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer.

Abstract translation: 倒装芯片半导体器件具有在其上形成有多个有源器件的衬底。 接触焊盘形成在与多个有源器件电接触的衬底上。 在衬底和中间导电层上形成钝化层。 在钝化层上形成粘合剂层。 在粘合剂层上形成阻挡层。 在阻挡层上形成润湿层。 去除第一区域中的阻挡层和润湿层，同时维持第二区域中的阻挡层，润湿层和粘合剂层。 保持第一区域中的钝化层上的粘合剂层直到形成焊料凸点。 通过将粘合剂层保持在钝化层上方直到形成焊料凸点，在钝化层中发生较少的破裂。

公开(公告)号：US08241952B2

公开(公告)日：2012-08-14

申请号：US12713018

申请日：2010-02-25

Applicant: Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

Inventor： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

Abstract translation: 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US20120175771A1

公开(公告)日：2012-07-12

申请号：US13423782

申请日：2012-03-19

Applicant: Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

Inventor： Rui Huang ,  Heap Hoe Kuan ,  Yaojian Lin ,  Seng Guan Chow

IPC: H01L25/07 ,  H01L23/528

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/32 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/1134 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/92 ,  H01L2224/96 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03

Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.

Abstract translation: 通过在第一牺牲载体上形成导电层制成半导体器件。 在导电层上形成焊料凸块。 在第一载体，导电层和焊料凸块上沉积无流动的底部填充材料。 将半导体管芯或部件压缩成无流动底部填充材料以与导电层电接触。 无流动底部填充材料和第一焊料凸块的表面被平坦化。 第一互连结构形成在无流动底部填充材料的第一表面上。 第一互连结构电连接到焊料凸块。 在第一互连结构上安装第二牺牲载体。 第二互连结构形成在无流动底部填充材料的第二侧上。 第二互连结构电连接到第一焊料凸块。 半导体器件可以通过焊料凸块堆叠和电连接。

公开(公告)号：US08183087B2

公开(公告)日：2012-05-22

申请号：US12207332

申请日：2008-09-09

Applicant: Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

Inventor： Yaojian Lin ,  Jianmin Fang ,  Kang Chen ,  Haijing Cao

IPC: H01L21/00

CPC classification number: H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L2221/68372 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/1134 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a temporary carrier for supporting the semiconductor device. An integrated passive device (IPD) is mounted to the temporary carrier using an adhesive. The IPD includes a capacitor and a resistor and has a plurality of through-silicon vias (TSVs). A discrete component is mounted to the temporary carrier using the adhesive. The discrete component includes a capacitor. The IPD and the discrete component are encapsulated using a molding compound. A first metal layer is formed over the molding compound. The first metal layer is connected to the TSVs of the IPD and forms an inductor. The temporary carrier and the adhesive are removed, and a second metal layer is formed over the IPD and the discrete component. The second metal layer interconnects the IPD and the discrete component and forms an inductor. An optional interconnect structure is formed over the second metal layer.

Abstract translation: 通过提供用于支撑半导体器件的临时载体来制造半导体器件。 使用粘合剂将集成无源器件（IPD）安装到临时载体上。 IPD包括电容器和电阻器，并且具有多个穿硅通孔（TSV）。 使用粘合剂将分立的部件安装到临时载体上。 分立元件包括电容器。 使用模塑料封装IPD和分立组件。 在模塑料上形成第一金属层。 第一金属层连接到IPD的TSV并形成电感器。 去除临时载体和粘合剂，并且在IPD和分立组件上形成第二金属层。 第二金属层将IPD和分立元件互连并形成电感器。 在第二金属层上形成可选的互连结构。