公开(公告)号：US20150114688A1

公开(公告)日：2015-04-30

申请号：US14522316

申请日：2014-10-23

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Byung Ho KIM

IPC: H05K1/03 ,  H05K1/02 ,  H05K1/09

CPC classification number: H05K1/0271 ,  H05K1/0298 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/09972

Abstract: Disclosed herein is a printed circuit board having an improved structure of a dummy part to improve warpage strength of the printed circuit board, the printed circuit board including: a plurality of insulating layers built-up therein, the plurality of insulating layers including copper clad layers; and a product zone and a dummy zone formed at a central part and along an edge part of the insulating layers, respectively, wherein the copper clad layers included in each insulating layer are arranged in the dummy zone at predetermined intervals in a longitudinal direction.

Abstract translation: 本发明公开了一种印刷电路板，其具有改善的印刷电路板的翘曲强度的结构，该印刷电路板包括：多个绝缘层，其中包括多个绝缘层，包括铜包覆层 ; 以及分别形成在绝缘层的中心部分和边缘部分处的产品区域和虚拟区域，其中包含在每个绝缘层中的铜包层沿纵向方向以预定间隔布置在虚拟区域中。

公开(公告)号：US09011799B2

公开(公告)日：2015-04-21

申请号：US13572001

申请日：2012-08-10

Applicant: Burkhardt Reichmuth

Inventor： Burkhardt Reichmuth

IPC: G01F19/00 ,  G01L3/02 ,  H05K1/02 ,  G01F11/02 ,  B01L3/02 ,  G01N35/10 ,  H05K1/03

CPC classification number: H05K1/0296 ,  B01L3/0227 ,  B01L2200/087 ,  B01L2200/12 ,  G01F11/021 ,  G01N35/1002 ,  H05K1/0393 ,  H05K2201/053 ,  H05K2201/09027 ,  H05K2201/09063 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/0939 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09972 ,  H05K2201/10151

Abstract: The invention relates to a laboratory sample instrument with a cable holding space in which a printed circuit board cable device is arranged. The printed circuit board cable device has at least one printed circuit board with first and second sides and, arranged in succession, at least one first circuit board section, at least one second circuit board section and at least one third circuit board section, and with a number of conductor tracks arranged in parallel with respect to one another and extending from a first track section arranged in the first circuit board section, via the second circuit board section to the third circuit board section, in which a second track section is arranged, wherein, in the second circuit board section, at least one conductor track is arranged on the first side of the board and at least one track is arranged on the second side.

Abstract translation: 本发明涉及具有电缆保持空间的实验室样品仪器，其中布置有印刷电路板电缆装置。 印刷电路板电缆装置具有至少一个具有第一和第二侧面的印刷电路板，并且连续地布置有至少一个第一电路板部分，至少一个第二电路板部分和至少一个第三电路板部分，并且具有 多个导体轨道相对于彼此平行布置并且从布置在第一电路板部分中的第一轨道部分经由第二电路板部分延伸到布置有第二轨道部分的第三电路板部分， 其中，在所述第二电路板部分中，至少一个导体轨道布置在所述板的第一侧上，并且至少一个轨道布置在所述第二侧上。

公开(公告)号：US20150070849A1

公开(公告)日：2015-03-12

申请号：US14090445

申请日：2013-11-26

Applicant: Taiyo Yuden Co., Ltd.

Inventor： Masaya SHIMAMURA ,  Takehiko KAI ,  Eiji MUGIYA ,  Tetsuo SAJI ,  Hiroshi NAKAMURA

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15159 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H05K1/0215 ,  H05K1/0269 ,  H05K3/284 ,  H05K5/065 ,  H05K9/0037 ,  H05K9/0083 ,  H05K2201/09036 ,  H05K2201/09145 ,  H05K2201/09972 ,  H05K2201/1056 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: There is provided a circuit module including a circuit substrate having a mount surface; a mount component mounted on the mount surface; a sealing body formed on the mount surface, the sealing body covering the mount component and having a trench formed from a main surface of the sealing body to the mount surface; and a shield having an inner shield section formed within the trench and an outer shield section that covers the sealing body and the inner shield section, the outer shield section including a first section having a flat surface formed on the main surface of the shielding body and a second section formed on the inner shield section and protruded or sagged from the first section.

Abstract translation: 提供一种电路模块，包括具有安装表面的电路基板; 安装在安装表面上的安装部件; 所述密封体形成在所述安装表面上，所述密封体覆盖所述安装部件，并且具有从所述密封体的主表面到所述安装表面形成的沟槽; 以及屏蔽体，其具有形成在所述沟槽内的内屏蔽部和覆盖所述密封体和所述内屏蔽部的外屏蔽部，所述外屏蔽部具有形成在所述屏蔽体的主表面上的平坦面的第一部， 形成在所述内屏蔽部上并从所述第一部分突出或下垂的第二部分。

公开(公告)号：US08975750B2

公开(公告)日：2015-03-10

申请号：US14455336

申请日：2014-08-08

Applicant: Renesas Electronics Corporation

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L21/00 ,  H01L21/30 ,  H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US08975735B2

公开(公告)日：2015-03-10

申请号：US13962622

申请日：2013-08-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Höglauer

IPC: H01L23/02 ,  H01L23/34 ,  H01L23/06 ,  H01L21/00 ,  H05K7/00 ,  H01L23/522 ,  H01L29/778

CPC classification number: H01L23/5226 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/2003 ,  H01L29/778 ,  H01L2224/48091 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/0761 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09972 ,  H01L2924/00014

Abstract: A redistribution board includes a first conductive layer including a redistribution structure for low voltage signals, a second conductive layer including a redistribution structure for high voltage signals, and a non-conductive layer. The second conductive layer is spaced apart from the first conductive layer by the non-conductive layer. The redistribution board further includes a conductive connector extending from a mounting surface of the redistribution board to the second conductive layer. The conductive connector is surrounded by a low voltage trace of the first conductive layer.

Abstract translation: 再分配板包括：第一导电层，包括用于低电压信号的再分配结构;第二导电层，包括用于高电压信号的再分配结构;以及非导电层。 第二导电层通过非导电层与第一导电层间隔开。 再分配板还包括从再分布板的安装表面延伸到第二导电层的导电连接器。 导电连接器被第一导电层的低电压迹线围绕。

公开(公告)号：US20140262499A1

公开(公告)日：2014-09-18

申请号：US13804575

申请日：2013-03-14

Applicant: BOULDER WIND POWER, INC.

Inventor： James S. Smith ,  James D. Duford ,  Stephane Eisen ,  James D. Jore ,  Brian Sullivan

IPC: H01B5/00 ,  H01R4/00

CPC classification number: H01R4/00 ,  H02K3/26 ,  H02K7/1838 ,  H02K21/24 ,  H05K1/0201 ,  H05K1/0216 ,  H05K1/165 ,  H05K3/462 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/093 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/09972 ,  H05K2201/10272 ,  H05K2201/10295

Abstract: In some embodiments, a system includes a first portion, a second portion, and a third portion of an electrical conductor. Each portion is electrically coupled to the other two portions. The first, second, and third portions are configured such that substantially no current induced in and/or supplied to the first portion is conducted to the third portion of the electrical conductor. The third portion of the electrical conductor is also thermally coupled to the first and second portions of the electrical conductor. The third portion of the electrical conductor is configured to transfer thermal energy from the first portion of the electrical conductor to an edge portion of the laminated composite assembly.

Abstract translation: 在一些实施例中，系统包括电导体的第一部分，第二部分和第三部分。 每个部分电耦合到另外两个部分。 第一，第二和第三部分被配置为使得基本上没有在第一部分中引入和/或提供给第一部分的电流被传导到电导体的第三部分。 电导体的第三部分也热耦合到电导体的第一和第二部分。 电导体的第三部分被配置为将热能从电导体的第一部分传递到层压复合组件的边缘部分。

公开(公告)号：US20140254108A1

公开(公告)日：2014-09-11

申请号：US13792092

申请日：2013-03-10

Applicant: QUALCOMM INCORPORATED

Inventor： Yang ZHANG ,  Jack B. STEENSTRA

IPC: H05K1/02 ,  H05K3/32 ,  H05K3/46 ,  H05K7/02

CPC classification number: H05K1/0298 ,  H05K1/0201 ,  H05K7/02 ,  H05K2201/09663 ,  H05K2201/09709 ,  H05K2201/09972 ,  H05K2201/10098 ,  H05K2201/10151 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A printed circuit board assembly for reducing the impact of heat generated from circuitry within a handheld or non-handheld device is provided. The printed circuit board assembly may include a printed circuit board comprising a plurality of conductive layers and a plurality of dielectric layers where each dielectric layer is disposed between a pair of conductive layers. Each conductive layer may include a first portion and a second portion separated by a gap where the gaps in the alternating conductive layers are misaligned. The first portion of each conductive layer may be substantially thermally isolated from the second portion of each conductive layer.

Abstract translation: 提供了一种用于减少由手持设备或非手持设备内的电路产生的热量的影响的印刷电路板组件。 印刷电路板组件可以包括印刷电路板，其包括多个导电层和多个电介质层，其中每个电介质层设置在一对导电层之间。 每个导电层可以包括由交替导电层中的间隙不对准的间隙分开的第一部分和第二部分。 每个导电层的第一部分可以与每个导电层的第二部分基本上热隔离。

公开(公告)号：US20140216802A1

公开(公告)日：2014-08-07

申请号：US13761172

申请日：2013-02-07

Applicant: Yu-Ru Chang ,  Yu-Fang Hsia ,  Ling-Chih Chou

Inventor： Yu-Ru Chang ,  Yu-Fang Hsia ,  Ling-Chih Chou

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/60 ,  H01L2924/0002 ,  H05K1/0286 ,  H05K1/11 ,  H05K1/18 ,  H05K3/10 ,  H05K3/22 ,  H05K3/4694 ,  H05K2201/09127 ,  H05K2201/09972 ,  H05K2203/0228 ,  Y10T29/49155 ,  H01L2924/00

Abstract: The present invention discloses a package substrate layout design to achieve multiple substrate functions for engineering development and verification. The substrate layout contains a connection structure to connect to a plurality of power/ground domains on the package substrate. With different combination of the cutting lines on the package substrate, the invention can achieve multiple substrate functions without impacting the customer's PCB or system board design and provide cost effective and fast cycle time for engineering development phase.

Abstract translation: 本发明公开了一种封装基板布局设计，以实现用于工程开发和验证的多个基板功能。 衬底布局包含连接到封装衬底上的多个电源/接地区域的连接结构。 通过封装基板上切割线的不同组合，本发明可以实现多种基板功能，而不会影响客户的PCB或系统板设计，并为工程开发阶段提供成本效益和快速的周期时间。

公开(公告)号：US20140133075A1

公开(公告)日：2014-05-15

申请号：US14162002

申请日：2014-01-23

Applicant: Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

Inventor： Md Altaf Hossain ,  Cliff C. Lee ,  David W. Browning ,  Itai M. Pines ,  Brian P. Kelly

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2924/12042 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09972 ,  H05K2201/10378 ,  H01L2924/014 ,  H01L2924/00

Abstract: The present disclosure relates to microelectronic substrates, such as interposers, motherboards, test platforms, and the like, that are fabricated to have overlapping connection zones, such that different microelectronic devices, such as microprocessors, chipsets, graphics processing devices, wireless devices, memory devices, application specific integrated circuits, and the like, may be alternately attached to the microelectronic substrates to form functional microelectronic packages.

Abstract translation: 本公开涉及被制造为具有重叠的连接区域的微电子衬底，例如插入件，母板，测试平台等，使得不同的微电子器件，例如微处理器，芯片组，图形处理器件，无线器件，存储器 设备，专用集成电路等可以交替地附接到微电子基板以形成功能微电子封装。

公开(公告)号：US20140126857A1

公开(公告)日：2014-05-08

申请号：US13951633

申请日：2013-07-26

Applicant: NITTO DENKO CORPORATION

Inventor： Shotaro Masuda ,  Toshikazu Baba ,  Yasuto Ishimaru

IPC: G02B6/12

CPC classification number: G02B6/12002 ,  G02B6/138 ,  H05K1/0274 ,  H05K1/028 ,  H05K2201/09236 ,  H05K2201/09909 ,  H05K2201/09972 ,  H05K2203/1572

Abstract: An opto-electric hybrid board which is capable of significantly reducing stresses applied to a bent portion thereof is provided. The opto-electric hybrid board includes a stacked electric circuit board and an optical waveguide. The electric circuit board includes an insulative layer having front and back surfaces, electrical interconnect lines formed on the front surface of the insulative layer, and an insulative coverlay formed on the front surface of the insulative layer and for covering and protecting the electrical interconnect lines. The optical waveguide includes a first cladding layer having a front surface, cores formed in a pattern on the front surface of the first cladding layer, and a second cladding layer covering the cores. Part of the opto-electric hybrid board is defined as a to-be-bent portion in which the coverlay and the optical waveguide are disposed in non-overlapping relation.

Abstract translation: 提供能够显着降低施加到其弯曲部分的应力的光电混合板。 光电混合基板包括堆叠电路板和光波导。 该电路板包括具有前表面和后表面的绝缘层，形成在绝缘层的前表面上的电互连线，以及形成在绝缘层的前表面上并用于覆盖和保护电互连线的绝缘覆盖层。 光波导包括具有前表面的第一包层，在第一包层的表面上以图案形成的芯和覆盖芯的第二包覆层。 光电混合板的一部分被定义为其中覆盖层和光波导以非重叠关系设置的弯曲部分。