公开(公告)号：US09015936B2

公开(公告)日：2015-04-28

申请号：US13891204

申请日：2013-05-10

Applicant: Zhen Ding Technology Co., Ltd.

Inventor： Che-Wei Hsu ,  Shih-Ping Hsu

IPC: H01K3/10 ,  H05K3/02 ,  H05K3/10 ,  H05K1/00 ,  H05K3/00 ,  H05K3/46 ,  H01L23/498 ,  H01L21/48 ,  H05K3/42

CPC classification number: H05K3/108 ,  H01L21/486 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K3/0097 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2203/1545 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for manufacturing an IC substrate includes following steps: providing a roll of double-sided flexible copper clad laminate; converting the roll of double sided flexible copper clad laminate into a roll of double sided flexible wiring board in a roll to roll manner; cutting the roll of double-sided flexible wiring board into a plurality of separate sheets of double sided flexible wiring board; forming first and second rigid insulating layers on the first and second wiring layers of each sheet of double sided flexible wiring board; forming third and fourth wiring layers on the first and second rigid insulating layers, and electrically connecting the first and third wiring layers, and electrically connecting the fourth and second wiring layers, thereby obtaining a sheet of substrate having a plurality of IC substrate units; and cutting the sheet of substrate into separate IC substrate units.

Abstract translation: 制造IC基板的方法包括以下步骤：提供一卷双面柔性覆铜层压板; 将双面柔性覆铜层压板卷以卷对卷方式转换成双面柔性布线板卷; 将双面柔性布线板的卷筒切割成多个单独的双面柔性布线板; 在每张双面柔性布线板的第一和第二布线层上形成第一和第二刚性绝缘层; 在第一和第二刚性绝缘层上形成第三和第四布线层，并且电连接第一和第三布线层，并电连接第四和第二布线层，从而获得具有多个IC基板单元的基片; 并将基片切割成单独的IC基片单元。

公开(公告)号：US20150109748A1

公开(公告)日：2015-04-23

申请号：US14360906

申请日：2011-11-29

Applicant: Zhongyao Yu ,  Xia Zhang

Inventor： Zhongyao Yu ,  Xia Zhang

IPC: H05K1/18 ,  H05K3/46 ,  H01L21/78 ,  H05K1/11 ,  H01L25/00 ,  H01L25/16

CPC classification number: H05K1/188 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24135 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/92144 ,  H01L2924/12042 ,  H05K1/115 ,  H05K1/185 ,  H05K3/46 ,  H05K3/4652 ,  H05K2201/0137 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/09509 ,  H01L2924/00

Abstract: An active chip package substrate and a method for preparing the same. The active chip package substrate includes: a core board; at least one upper active chip, embedded in the core board and having an active surface facing toward a lower surface of the core board, the upper active chip being an active bare chip; and at least one lower active chip, embedded in the core board and having an active surface facing toward an upper surface of the core board, the lower active chip being an active bare chip.

Abstract translation: 一种有源芯片封装基板及其制备方法。 有源芯片封装基板包括：芯板; 至少一个上有源芯片，嵌入在所述芯板中并且具有面向所述芯板的下表面的有源表面，所述上有源芯片是有源裸芯片; 以及至少一个下部有源芯片，嵌入在所述芯板中并且具有面向所述芯板的上表面的有源表面，所述下部有源芯片是有源裸芯片。

公开(公告)号：US20150075851A1

公开(公告)日：2015-03-19

申请号：US14548725

申请日：2014-11-20

Applicant: IBIDEN CO., LTD.

Inventor： Masahiro KANEKO ,  Satoru KOSE ,  Hirokazu HIGASHI

IPC: H05K3/42 ,  H05K1/03 ,  H05K3/22 ,  H05K1/11

CPC classification number: H05K3/42 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2224/85001 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/0313 ,  H05K1/113 ,  H05K1/115 ,  H05K3/007 ,  H05K3/108 ,  H05K3/22 ,  H05K3/388 ,  H05K2201/0344 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2203/072 ,  H05K2203/1377 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract translation: 印刷电路板包括具有贯通孔的层间树脂绝缘层，形成在层间树脂绝缘层的第一表面上的导电电路，形成在层间树脂绝缘层的穿透孔中并与导电 电路，形成在填充的通路导体的第一表面上并具有无电解电镀结构的第一表面处理涂层结构和形成在填充通孔导体的第二表面上的第二表面处理涂层结构，该第二表面处理涂层结构相对于 涉及第一表面处理涂层结构并具有化学镀层结构。 填充的通孔导体包括形成在穿透孔的侧壁上的第一导电层和填充穿透孔的电镀材料，第一表面处理涂层结构的厚度与第二表面处理涂层的厚度不同 结构体。

公开(公告)号：US20150013901A1

公开(公告)日：2015-01-15

申请号：US14327916

申请日：2014-07-10

Applicant: HSIO TECHNOLOGIES, LLC

Inventor： JAMES RATHBURN

IPC: H05K3/46 ,  H05K3/12 ,  H01L21/768 ,  H05K3/18

CPC classification number: H01L21/76877 ,  B33Y80/00 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0393 ,  H05K1/16 ,  H05K3/0005 ,  H05K3/4069 ,  H05K3/421 ,  H05K3/429 ,  H05K3/465 ,  H05K3/4658 ,  H05K2201/09272 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/1476 ,  H01L2924/00014

Abstract: A system and method for “pixelating” a three-dimensional circuit structure into a three-dimensional matrix of cubes that are located with respect to a coordinate system. The design step is typically performed on a conventional computer using computer aided design software that pixelates the proposed circuit structure into an array of uniformly sized cube. The fabrication process involves adding and subtracting bulk materials from the individual cubic positions within the pixelated representation of the circuit structure. Various existing and new techniques can be used to add or subtract bulk materials as the cubic positions within the matrix to construct the circuit structure.

Abstract translation: 将三维电路结构“像素化”为相对于坐标系定位的三维矩阵的三维矩阵的系统和方法。 设计步骤通常在使用计算机辅助设计软件的常规计算机上执行，将所提出的电路结构像素化为均匀尺寸的立方体的阵列。 制造过程包括在电路结构的像素化表示内从各个立方体位置添加和减去大量材料。 可以使用各种现有技术和新技术将体积材料作为立方体位置加入或减去以构成电路结构。

公开(公告)号：US08925194B2

公开(公告)日：2015-01-06

申请号：US13219169

申请日：2011-08-26

Applicant: Michimasa Takahashi ,  Masakazu Aoyama

Inventor： Michimasa Takahashi ,  Masakazu Aoyama

IPC: H01K3/10 ,  H05K3/00 ,  H01L23/02 ,  H05K1/00 ,  H05K1/03 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4691 ,  H05K1/0218 ,  H05K3/0035 ,  H05K3/4652 ,  H05K3/4664 ,  H05K2201/0187 ,  H05K2201/0715 ,  H05K2201/09127 ,  H05K2201/09509 ,  Y10T29/49124 ,  Y10T29/49165

Abstract: A method of manufacturing a flex-rigid wiring board includes disposing a non-flexible substrate and a flexible board side by side in the horizontal direction of the substrate and board such that an end of the substrate is positioned adjacent to an end of the board and forms boundary between the board and the substrate with respect to the end of the board, covering the boundary between the board and the substrate with an insulating layer such that the insulating layer is positioned on the board and the substrate across the boundary, forming a second conductor pattern on the insulating layer, forming a via hole which passes through the insulating layer and reaches a first conductor pattern of the board, and plating the via hole such that a via conductor connecting the first and second patterns. The flexible board includes a flexible substrate and the first pattern formed over the substrate.

Abstract translation: 制造柔性刚性布线板的方法包括在基板和板的水平方向上并排设置非柔性基板和柔性基板，使得基板的端部邻近板的端部定位， 在板和基板之间形成相对于板的端部的边界，用绝缘层覆盖板和基板之间的边界，使得绝缘层位于板上并且基板跨越边界，形成第二个 形成绝缘层上的导体图案，形成穿过绝缘层并到达板的第一导体图形的通孔，并且对通孔进行电镀，使得连接第一和第二图案的通孔导体。 柔性板包括柔性基板和形成在基板上的第一图案。

公开(公告)号：US20140312101A1

公开(公告)日：2014-10-23

申请号：US14318403

申请日：2014-06-27

Applicant: RAVINDRA V. TANIKELLA

Inventor： RAVINDRA V. TANIKELLA

IPC: H01L23/29 ,  H01L21/56

CPC classification number: H01L23/49894 ,  C08F283/04 ,  C08G73/121 ,  C08K3/36 ,  C08K9/10 ,  C08K2201/011 ,  C08L79/08 ,  C08L2666/66 ,  H01L21/4857 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/296 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/18161 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/28 ,  H05K3/421 ,  H05K3/422 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/1163 ,  H05K2203/121 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts). In one embodiment, the solder resist opening walls have a wettable layer generated through laser assisted seeding so that there is no gap between the solder resist opening walls and no underfill in the solder resist opening.

Abstract translation: 用于微电子封装的高度可靠的互连。 在一个实施例中，积聚互连中的电介质层具有玻璃化转变温度的等级; 并且稍后施加的电介质层在低于较早施加的电介质层的玻璃化转变温度的温度下被层压。 在一个实施方案中，通过热固化工艺增加了积聚互连中早期施加的介电膜的玻璃化转变温度，以超过用于层压后来施加的电介质膜的温度。 在一个实施方案中，在层压聚酰亚胺材料的膜（例如通过催化剂的密封剂的光化学或热降解）之后，形成具有嵌入催化剂以促进交联的聚酰亚胺材料。 在一个实施例中，阻焊剂开口壁具有通过激光辅助接种产生的可湿性层，使得阻焊剂开口壁之间没有间隙，并且在阻焊剂开口中没有底部填充物。

公开(公告)号：US08813353B2

公开(公告)日：2014-08-26

申请号：US12785037

申请日：2010-05-21

Applicant: Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

Inventor： Yasuhiko Inui ,  Takamichi Ogawa ,  Seiji Ichiyanagi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K3/20 ,  H01L23/498 ,  H05K1/16 ,  H01L23/50 ,  H01L21/48 ,  H05K1/09 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/092 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/09736 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4981 ,  Y10T407/1946 ,  Y10T407/1948 ,  H01L2924/00

Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 μm, the dielectric layer has a thickness of from 0.3 to 5 μm, and the conductor layer has a thickness of from 0.3 to 10 μm. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 μm, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 μm, and a minimum via pitch is from 100 to 350 μm.

Abstract translation: 包括依次设置的金属箔，电介质层和导体层的电介质结构体，其中金属箔的厚度为10〜40μm，电介质层的厚度为0.3〜5μm，导体 层的厚度为0.3〜10μm。 电介质结构具有彼此分离并且穿透介电层和导体层两者的多个通孔。 电介质层的通孔具有不同的直径，范围为100〜300μm，导体层的通孔的直径大于电介质层的通孔的直径为5〜50μm ，最小通孔间距为100〜350μm。

公开(公告)号：US08785790B2

公开(公告)日：2014-07-22

申请号：US13293698

申请日：2011-11-10

Applicant: Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Hiroaki Sato ,  Philip Damberg

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Belgacem Haba ,  Hiroaki Sato ,  Philip Damberg

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K1/115 ,  H01L23/14 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/03 ,  H05K1/09 ,  H05K3/42 ,  H05K2201/0141 ,  H05K2201/0175 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2203/025 ,  H05K2203/1105 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A component includes a support structure having first and second spaced-apart and parallel surfaces and a plurality of conductive elements extending in a direction between the first and second surfaces. Each conductive element contains an alloy of a wiring metal selected from the group consisting of copper, aluminum, nickel and chromium, and an additive selected from the group consisting of Gallium, Germanium, Indium, Selenium, Tin, Sulfur, Silver, Phosphorus, and Bismuth. The alloy has a composition that varies with distance in at least one direction across the conductive element. A concentration of the additive is less than or equal to 5% of the total atomic mass of the conductive element, and a resistivity of the conductive element is between 2.5 and 30 micro-ohm-centimeter.

Abstract translation: 组件包括具有第一和第二间隔开并平行表面的支撑结构以及沿第一和第二表面之间的方向延伸的多个导电元件。 每个导电元件包含选自铜，铝，镍和铬的布线金属的合金和选自由镓，锗，铟，硒，锡，硫，银，磷和 铋。 该合金具有随导电元件的至少一个方向上的距离而变化的组成。 添加剂的浓度小于或等于导电元件的总原子质量的5％，并且导电元件的电阻率在2.5至30微欧姆厘米之间。

公开(公告)号：US08772921B2

公开(公告)日：2014-07-08

申请号：US13347683

申请日：2012-01-10

Applicant: Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

Inventor： Chin Hock Toh ,  Yao Huang Huang ,  Ravi Kanth Kolan ,  Wei Liang Yuan ,  Susanto Tanary ,  Yi Sheng Anthony Sun

IPC: H01L23/02

CPC classification number: H01L21/563 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/15311 ,  H05K3/3478 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09572 ,  H05K2201/10378 ,  H05K2203/043 ,  Y10T29/49155 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An interposer is presented. The interposer includes an interposer base having first and second surfaces. A redistribution layer is disposed on a first surface of the interposer base. The interposer has at least one interposer pad coupled to the redistribution layer. It also includes at least one interposer contact on the second surface. The interposer contact is electrically coupled to the interposer pad via the redistribution layer. The interposer also includes at least one interposer via through the interposer base for coupling the interposer contact to the redistribution layer. The interposer via includes reflowed conductive material of the interposer contact.

Abstract translation: 介绍了插件。 插入器包括具有第一和第二表面的插入器基座。 再分配层设置在插入器基座的第一表面上。 插入器具有耦合到再分配层的至少一个插入器焊盘。 它还包括在第二表面上的至少一个中介层接触。 插入器触点通过再分配层电耦合到插入器衬垫。 插入器还包括通过插入器基座的至少一个插入器，用于将插入器触点耦合到再分配层。 插入器通孔包括内插器接触件的回流导电材料。

公开(公告)号：US08763241B2

公开(公告)日：2014-07-01

申请号：US13239487

申请日：2011-09-22

Applicant: Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

Inventor： Yasushi Inagaki ,  Motoo Asai ,  Dongdong Wang ,  Hideo Yabashi ,  Seiji Shirai

IPC: H05K3/30

CPC classification number: H05K1/181 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L24/17 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/187 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/063 ,  Y02P70/611 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49146 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.

Abstract translation: 一种制造印刷电路板的方法，包括提供具有树脂板的第一树脂基板和形成在树脂板的表面上的电路图案，提供具有树脂板和形成在树脂板中的容纳部分的第二树脂基板 第二基板，利用接合材料将电容器的电极连接到第一基板的电路图案，使得电容器安装到第一基板，通过接合树脂层将第二基板附着到树脂基板，使得电容器 在第一基板上容纳在第二基板的容纳部分中，并且在第一基板中形成通孔，使得通孔与第二基板的容纳部分中的电容器的电极电连接。