公开(公告)号：US20170196133A1

公开(公告)日：2017-07-06

申请号：US15314914

申请日：2015-05-22

Applicant: Sharp Kabushiki Kaisha

Inventor： Katsuhiro YAMAGUCHI ,  Nobuhiro NAKATA ,  Yukinori MASUDA ,  Tomoki TAKAHARA

IPC: H05K13/04 ,  H05K3/00 ,  H01L23/00 ,  H05K1/11

CPC classification number: H05K13/0469 ,  G02F1/13454 ,  H01L24/03 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/29444 ,  H01L2224/2949 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75312 ,  H01L2224/75744 ,  H01L2224/75981 ,  H01L2224/75985 ,  H01L2224/81048 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81204 ,  H01L2224/81234 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81466 ,  H01L2224/81903 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83204 ,  H01L2224/83234 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/111 ,  H05K3/0055 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83

Abstract: An array substrate includes a driver, a glass substrate having a driver mounting section where the driver is mounted, an anisotropic conductive material that is interposed between the driver and driver mounting section so as to electrically connect both and that at least includes a binder made of a thermosetting resin and conductive particles in the binder, and a heat supply part provided on at least the driver mounting section of the glass substrate for supplying heat to the anisotropic conductive material.

公开(公告)号：US09620471B2

公开(公告)日：2017-04-11

申请号：US14723378

申请日：2015-05-27

Applicant: Infineon Technologies Americas Corp.

Inventor： Martin Standing ,  Robert J. Clarke

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/482 ,  H01L23/29 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L24/33 ,  H01L23/296 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/4951 ,  H01L23/49562 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/41725 ,  H01L29/4232 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29611 ,  H01L2224/29644 ,  H01L2224/2969 ,  H01L2224/81054 ,  H01L2224/8121 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0715 ,  H01L2924/1032 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/186 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/29075 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A power semiconductor package that includes a semiconductor die having at least two power electrodes and a conductive clip electrically and mechanically coupled to each power electrode.

公开(公告)号：US09620388B2

公开(公告)日：2017-04-11

申请号：US14941865

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： You Chye How ,  Maria Christina Bernardo Violante

IPC: H01L21/00 ,  H01L21/48 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/495 ,  H01L21/683 ,  H01L25/065

CPC classification number: H01L21/4821 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/6836 ,  H01L23/00 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49575 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/94 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68377 ,  H01L2224/27003 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1515 ,  H01L2924/181 ,  H01L2924/301 ,  H01L2924/0665 ,  H01L2224/45099 ,  H01L2224/27 ,  H01L2924/00 ,  H01L2924/0781

Abstract: A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed.

公开(公告)号：US09613934B2

公开(公告)日：2017-04-04

申请号：US14621936

申请日：2015-02-13

Applicant: INTEL CORPORATION

Inventor： Sandeep Razdan ,  Edward R. Prack ,  Sairam Agraharam ,  Robert L. Sankman ,  Shan Zhong ,  Robert M. Nickerson

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  C09J9/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  C09J9/02 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49866 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/5329 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/13005 ,  H01L2224/13025 ,  H01L2224/16113 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29078 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/2939 ,  H01L2224/29411 ,  H01L2224/29439 ,  H01L2224/29444 ,  H01L2224/29447 ,  H01L2224/29455 ,  H01L2224/29499 ,  H01L2224/73104 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13613 ,  H01L2924/014 ,  H01L2924/207 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations of interconnect structures having a polymer core in integrated circuit (IC) package assemblies. In one embodiment, an apparatus includes a first die having a plurality of transistor devices disposed on an active side of the first die and a plurality of interconnect structures electrically coupled with the first die, wherein individual interconnect structures of the plurality of interconnect structures have a polymer core, and an electrically conductive material disposed on the polymer core, the electrically conductive material being configured to route electrical signals between the transistor devices of the first die and a second die. Other embodiments may be described and/or claimed.

公开(公告)号：US09613930B2

公开(公告)日：2017-04-04

申请号：US14064093

申请日：2013-10-25

Applicant: Infineon Technologies AG

Inventor： Petteri Palm

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L24/89 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/24 ,  H01L24/31 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/05018 ,  H01L2224/08112 ,  H01L2224/08137 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/80031 ,  H01L2224/80488 ,  H01L2224/80801 ,  H01L2224/8082 ,  H01L2224/8085 ,  H01L2224/80904 ,  H01L2224/8203 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/83205 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/83851 ,  H01L2224/83889 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/141 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US09607960B1

公开(公告)日：2017-03-28

申请号：US14983506

申请日：2015-12-29

Applicant: Industrial Technology Research Institute

Inventor： Yi-Cheng Peng ,  Ming-Hua Yeh

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L24/32 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/4985 ,  H01L24/05 ,  H01L24/29 ,  H01L2224/04026 ,  H01L2224/05017 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/29005 ,  H01L2224/29082 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29344 ,  H01L2224/29355 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/83385 ,  H01L2224/83851 ,  H01L2924/00012

Abstract: A bonding structure comprising a contact pad, an anisotropic conductive film (ACF) and a contact structure is provided. The contact pad includes at least one recess, wherein a thickness of the contact pad is T, and a width of the at least one recess is B, The ACF is disposed on the contact pad and includes a plurality of conductive particles; each of the conductive particles is disposed in the at least one recess. A diameter of the conductive particles is A, and A is larger than B and T and satisfies B≦2(AT−T2)1/2. The contact structure is disposed on the ACF and electrically connected to the contact pad via the conductive particles. The disclosure also provides a flexible device including a substrate, a patterned insulating layer, at least one contact pad, ACF, and a contact structure.

公开(公告)号：US20170076134A1

公开(公告)日：2017-03-16

申请号：US15156950

申请日：2016-05-17

Applicant: J-METRICS TECHNOLOGY Co., Ltd.

Inventor： WEI-TING LIN ,  SHIH-CHUN KUO

IPC: G06K9/00

CPC classification number: G06K9/00053 ,  G06K9/00013 ,  H01L23/3121 ,  H01L23/60 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/8185 ,  H01L2224/83192 ,  H01L2224/83851 ,  H01L2924/00014 ,  H01L2924/15158 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A fingerprint sensing unit includes a carrier substrate, a fingerprint sensing chip on an upper surface of the carrier substrate, a molding layer, a light-pervious cover layer on the molding layer, and an adhesive layer between the light-pervious cover layer and the molding layer. The fingerprint sensing chip is electrically connected to the carrier substrate. The molding layer covers the fingerprint sensing chip.

Abstract translation: 指纹感测单元包括载体基板，载体基板的上表面上的指纹感测芯片，成型层，成型层上的透光性覆盖层，以及透光性覆盖层和透光性覆盖层之间的粘合剂层 成型层。 指纹感测芯片电连接到载体衬底。 成型层覆盖指纹感测芯片。

公开(公告)号：US20170069595A1

公开(公告)日：2017-03-09

申请号：US15257427

申请日：2016-09-06

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05687 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13193 ,  H01L2224/1403 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16146 ,  H01L2224/271 ,  H01L2224/2733 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/27849 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/3201 ,  H01L2224/32105 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75102 ,  H01L2224/8109 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8309 ,  H01L2224/83101 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83851 ,  H01L2224/83862 ,  H01L2224/8388 ,  H01L2224/9211 ,  H01L2224/9212 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/381 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/0675 ,  H01L2924/0635 ,  H01L2924/00012 ,  H01L2924/069 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2224/27

Abstract: 3D joining of microelectronic components and a conductively self-adjusting anisotropic matrix are provided. In an implementation, an adhesive matrix automatically makes electrical connections between two surfaces that have electrical contacts, and bonds the two surfaces together. Conductive members in the adhesive matrix are aligned to automatically establish electrical connections between at least partially aligned contacts on each of the two surfaces while providing nonconductive adhesion between parts of the two surfaces lacking aligned contacts. An example method includes forming an adhesive matrix between two surfaces to be joined, including conductive members anisotropically aligned in an adhesive medium, then pressing the two surfaces together to automatically connect corresponding electrical contacts that are at least partially aligned on the two surfaces. The adhesive medium in the matrix secures the two surfaces together.

Abstract translation: 提供了微电子部件的3D连接和导电自调节各向异性矩阵。 在一个实施方案中，粘合剂基质自动地在具有电接触的两个表面之间进行电连接，并将两个表面粘合在一起。 粘合剂基体中的导电构件对准以在两个表面中的每一个上的至少部分对准的触点之间自动建立电连接，同时在缺少对准的触点的两个表面的部分之间提供非导电粘附。 一个示例性方法包括在待接合的两个表面之间形成粘合剂基体，包括在粘合剂介质中各向异性排列的导电构件，然后将两个表面压在一起，以自动连接在两个表面上至少部分对准的对应的电触头。 基体中的粘合剂介质将两个表面固定在一起。

公开(公告)号：US20170012603A1

公开(公告)日：2017-01-12

申请号：US15204391

申请日：2016-07-07

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Russ Alan REISNER ,  John C. BALDWIN

IPC: H03H9/05 ,  H01L23/552 ,  H03H9/46 ,  H01L23/66 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065

CPC classification number: H03H9/0566 ,  H01L23/3114 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83851 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06555 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/19105 ,  H03H9/46 ,  H03H9/706 ,  H03H9/725 ,  H04B1/04 ,  H04B1/16 ,  H04B1/48

Abstract: Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.

Abstract translation: 与堆叠双工器有关的设备和方法。 在一些实施例中，组件可以包括具有射频（RF）屏蔽的第一晶片级封装（WLP）器件。 组件还可以包括具有RF屏蔽的第二WLP设备，第二WLP设备位于第一WLP设备之上，使得第二WLP设备的RF屏蔽电连接到第一WLP设备的RF屏蔽。

公开(公告)号：US09533878B2

公开(公告)日：2017-01-03

申请号：US14567801

申请日：2014-12-11

Applicant: ANALOG DEVICES, INC.

Inventor： Thomas M. Goida ,  Kathleen O'Donnell ,  Michael Delaus

IPC: H01L23/495 ,  B81B7/00 ,  B81C1/00 ,  H01L25/18 ,  H01L23/498 ,  H01L23/13 ,  H01L23/34 ,  H01L23/00

CPC classification number: B81B7/0074 ,  B81B7/0054 ,  B81C1/00238 ,  B81C1/00301 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06572 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/3025 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Various low stress compact device packages are disclosed herein. An integrated device package can include a first integrated device die and a second integrated device die. An interposer can be disposed between the first integrated device die and the second integrated device die such that the first integrated device die is mounted to and electrically coupled to a first side of the interposer and the second integrated device die is mounted to and electrically coupled to a second side of the interposer. The first side can be opposite the second side. The interposer can comprise a hole through at least the second side of the interposer. A portion of the second integrated device die can extend into the hole.

Abstract translation: 本文公开了各种低应力小型器件封装。 集成器件封装可以包括第一集成器件管芯和第二集成器件管芯。 插入器可以设置在第一集成器件管芯和第二集成器件管芯之间，使得第一集成器件裸片安装到电连接到插入器的第一侧并且电连接到插入器的第一侧，并且第二集成器件管芯安装到电耦合到 插入器的第二面。 第一面可以与第二面相对。 插入器可以包括穿过插入件的至少第二侧的孔。 第二集成器件芯片的一部分可以延伸到孔中。