公开(公告)号：US20150155252A1

公开(公告)日：2015-06-04

申请号：US14399351

申请日：2013-05-07

Applicant: Heraeus Materials Technology GmbH & Co. KG

Inventor： Eugen Milke ,  Peter Prenosil ,  Sven Thomas

IPC: H01L23/00 ,  B21F9/00 ,  C22C21/00 ,  C22F1/08 ,  C22F1/04 ,  C22C9/00 ,  B32B15/01 ,  B23K1/00

CPC classification number: H01L24/45 ,  B21F9/005 ,  B23K1/0016 ,  B32B15/01 ,  C22C9/00 ,  C22C21/00 ,  C22F1/04 ,  C22F1/08 ,  H01B1/023 ,  H01B1/026 ,  H01L24/43 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/4312 ,  H01L2224/43125 ,  H01L2224/43848 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45541 ,  H01L2224/45565 ,  H01L2224/45617 ,  H01L2224/45624 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/4823 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85205 ,  H01L2224/85424 ,  H01L2224/859 ,  H01L2924/00011 ,  H01L2924/00015 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/01322 ,  H01L2924/1203 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/20305 ,  H01L2924/2076 ,  Y10T428/1275 ,  H01L2924/00014 ,  H01L2924/01201 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01205 ,  H01L2924/00 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011 ,  H01L2924/20111 ,  H01L2224/45139 ,  H01L2924/00012 ,  H01L2924/01049 ,  H01L2924/01006

Abstract: A wire, preferably a bonding wire for bonding in microelectronics, contains a copper core with a surface and coating layer containing aluminum superimposed over the surface of the copper core. The ratio of the thickness of the coating layer to the diameter of the copper core is from 0.05 to 0.2 μm. The wire has a diameter in the range of from 100 μm to 600 μm and specified standard deviations of the diameter of the copper core and of the thickness of the coating layer. The invention further relates to a process for making a wire, to a wire obtained by the process, to an electric device containing at least two elements and the wire, to a propelled device containing the electric device, and to a process of connecting two elements through the wire by wedge bonding.

Abstract translation: 电线，优选用于在微电子学中接合的接合线包含铜芯，其表面和包含铝的涂层叠加在铜芯的表面上。 涂层的厚度与铜芯的直径之比为0.05〜0.2μm。 线材的直径在100μm至600μm的范围内，铜芯直径和涂层厚度的特定标准偏差。 本发明还涉及一种将通过该方法获得的线材的线材制造成包含至少两个元件和电线的电气设备到包含电气设备的推进设备的方法，以及连接两个元件的过程 通过电线通过楔形键合。

公开(公告)号：US08441128B2

公开(公告)日：2013-05-14

申请号：US13210453

申请日：2011-08-16

Applicant: Daniel Domes

Inventor： Daniel Domes

IPC: H01L23/36 ,  H03K17/56

CPC classification number: H01L25/072 ,  H01L23/3735 ,  H01L23/49833 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/291 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48132 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2924/00011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01047 ,  H01L2924/1301 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/19107 ,  H01L2924/3011 ,  H02M7/003 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01005 ,  H01L2924/01201 ,  H01L2924/00014

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract translation: 半导体装置包括电路载体，接合线和至少N个半桥电路。 电路载体包括第一金属化层，第二金属化层，布置在第一金属化层和第二金属化层之间的中间金属化层，布置在中间金属化层和第二金属化层之间的第一绝缘层，以及第二绝缘层 层，布置在第一金属化层和中间金属化层之间。 每个半桥电路包括可控的第一半导体开关和可控的第二半导体开关。 每个半桥电路的第一半导体开关和第二半导体开关被布置在电路载体的第一金属化层的背离第二绝缘层的一侧。 接合线在第一接合位置处直接接合到电路载体的中间金属化层。

公开(公告)号：US20120292774A1

公开(公告)日：2012-11-22

申请号：US13519226

申请日：2011-01-20

Applicant: Shingo Itoh

Inventor： Shingo Itoh

IPC: H01L23/49

CPC classification number: H01L21/56 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49503 ,  H01L24/05 ,  H01L24/09 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05144 ,  H01L2224/05164 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48664 ,  H01L2224/48844 ,  H01L2224/48864 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01204 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/00012 ,  H01L2924/013 ,  H01L2924/0002 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/43848 ,  H01L2924/20751

Abstract: A semiconductor device of the present invention includes a semiconductor element having an electrode pad; a substrate over which the semiconductor element is mounted and has an electrical bonding part; and a bonding wire electrically connecting the electrode pad to the electrical bonding part, wherein a main metal component of the electrode pad is the same or different from a main metal component of the bonding wire, and when the main metal component of the electrode pad is different from the main metal components of the bonding wire, a rate of interdiffusion of the main metal components of the bonding wire and the electrode pad at a junction of the bonding wire and the electrode pad under a post-curing temperature of an encapsulating resin is lower than that of interdiffusion of gold (Au) and aluminum (Al) at a junction of aluminum (Al) and gold (Au) under the post-curing temperature.

Abstract translation: 本发明的半导体器件包括具有电极焊盘的半导体元件; 半导体元件安装在其上并具有电接合部的基板; 以及将电极焊盘电连接到电接合部分的接合线，其中电极焊盘的主金属部件与接合线的主金属部件相同或不同，并且当电极焊盘的主金属部件为 与接合线的主要金属成分不同，在封装树脂的后固化温度下，接合线和电极焊盘的接合处的接合线和电极焊盘的主金属成分的相互扩散率为 低于后固化温度下铝（Al）和金（Au）的接合处的金（Au）和铝（Al）的相互扩散。

公开(公告)号：US20120276693A1

公开(公告)日：2012-11-01

申请号：US13548120

申请日：2012-07-12

Applicant: Ralf Otremba ,  Xaver Schloegel ,  Khai Huat Jeffrey Low ,  Chee Soon Law

Inventor： Ralf Otremba ,  Xaver Schloegel ,  Khai Huat Jeffrey Low ,  Chee Soon Law

IPC: H01L21/50

CPC classification number: H01L23/49503 ,  B81C1/00301 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/00 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L24/84 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/37144 ,  H01L2224/40245 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45624 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73213 ,  H01L2224/78301 ,  H01L2224/7865 ,  H01L2224/84801 ,  H01L2224/85045 ,  H01L2224/85099 ,  H01L2224/851 ,  H01L2224/85205 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85801 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1301 ,  H01L2924/1304 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/2075 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2924/01016 ,  H01L2924/01026 ,  H01L2924/01201

Abstract: A module includes a semiconductor chip having at least a first terminal contact surface and a second terminal contact surface. A first bond element made of a material on the basis of Cu is attached to the first terminal contact surface, and a second bond element is attached to the second terminal contact surface. The second bond element is made of a material different from the material of the first bond element or is made of a type of bond element different from the type of the first bond element.

Abstract translation: 模块包括具有至少第一端子接触表面和第二端子接触表面的半导体芯片。 由基于Cu的材料制成的第一接合元件附接到第一端子接触表面，并且第二接合元件附接到第二端子接触表面。 第二结合元件由与第一结合元件的材料不同的材料制成，或者由不同于第一粘结元件的类型的粘结元件制成。

公开(公告)号：US20110115068A1

公开(公告)日：2011-05-19

申请号：US12949017

申请日：2010-11-18

Applicant: Hans Hartung ,  Dirk Siepe

Inventor： Hans Hartung ,  Dirk Siepe

IPC: H01L23/29

CPC classification number: H01L24/40 ,  H01L23/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/072 ,  H01L2224/04026 ,  H01L2224/05647 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/40095 ,  H01L2224/40225 ,  H01L2224/45014 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4846 ,  H01L2224/48472 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2224/83205 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/84205 ,  H01L2224/84801 ,  H01L2224/8484 ,  H01L2224/8485 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203

Abstract: A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 μm. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C.

Abstract translation: 功率半导体模块包括电路载体，该电路载体包括绝缘载体，该绝缘载体具有布置有金属化层的顶侧。 功率半导体芯片布置在金属化层的背离绝缘载体的一侧上，并且在功率半导体芯片的顶侧上背离电路载体，由铜或铜合金组成的上部芯片金属化层具有 大于或等于1μm的厚度。 由铜或铜合金构成的电连接导体在连接位置连接到上部芯片金属化。 灌封化合物从电路载体延伸到至少超过功率半导体芯片的顶侧，并且完全覆盖功率半导体芯片的顶侧，至少在连接位置的区域中包围连接导体，并具有穿透 根据DIN ISO 2137在25℃的温度下小于或等于30。

公开(公告)号：US20100239455A1

公开(公告)日：2010-09-23

申请号：US12408952

申请日：2009-03-23

Applicant: Jun-Der LEE

Inventor： Jun-Der LEE

IPC: C22C5/06 ,  B21C1/00

CPC classification number: B21C1/003 ,  B21C37/047 ,  B23K35/3006 ,  C22C5/06 ,  C22F1/14 ,  H01L24/43 ,  H01L24/45 ,  H01L2224/437 ,  H01L2224/43848 ,  H01L2224/43986 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/01046 ,  H01L2924/013 ,  H01L2924/01201 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2224/4321 ,  H01L2924/00015 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2924/01005

Abstract: A manufacturing method for a composite alloy bonding wire and products thereof. A primary material of Ag is melted in a vacuum melting furnace, and then a secondary metal material of Pd is added into the vacuum melting furnace and is co-melted with the primary material to obtain a Ag—Pd alloy solution. The obtained Ag—Pd alloy solution is drawn to obtain a Ag—Pd alloy wire. The Ag—Pd alloy wire is then drawn to obtain a Ag—Pd alloy bonding wire with a predetermined diameter.

Abstract translation: 一种复合合金接合线的制造方法及其制造方法。 Ag的主要材料在真空熔化炉中熔融，然后将Pd的二次金属材料加入到真空熔化炉中，并与主要材料共熔，得到Ag-Pd合金溶液。 将得到的Ag-Pd合金溶液拉伸，得到Ag-Pd合金丝。 然后将Ag-Pd合金线拉伸以获得具有预定直径的Ag-Pd合金接合线。

公开(公告)号：US07656045B2

公开(公告)日：2010-02-02

申请号：US11360336

申请日：2006-02-23

Applicant: Chu-Chung Lee ,  Kevin J. Hess

Inventor： Chu-Chung Lee ,  Kevin J. Hess

IPC: H01L29/40 ,  H01L21/44 ,  H01L21/4763

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48507 ,  H01L2224/48624 ,  H01L2224/48799 ,  H01L2224/85205 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01201 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2924/01203 ,  H01L2224/05147 ,  H01L2924/00 ,  H01L2224/48824 ,  H01L2924/01202

Abstract: A bond pad for an electronic device such as an integrated circuit makes electrical connection to an underlying device via an interconnect layer. The bond pad has a first layer of a material that is aluminum and copper and a second layer, over the first layer, of a second material that is aluminum and is essentially free of copper. The second layer functions as a cap to the first layer for preventing copper in the first layer from being corroded by residual chemical elements. A wire such as a gold wire may be bonded to the second layer of the bond pad.

Abstract translation: 用于诸如集成电路的电子器件的接合焊盘通过互连层电连接到下面的器件。 接合焊盘具有铝和铜的材料的第一层，在第一层上具有作为铝的第二材料的第二层，并且基本上不含铜。 第二层用作第一层的帽，以防止第一层中的铜被残留的化学元素腐蚀。 诸如金线的线可以结合到接合焊盘的第二层。

公开(公告)号：US07425767B2

公开(公告)日：2008-09-16

申请号：US11861290

申请日：2007-09-26

Applicant: Mou-Shiung Lin

Inventor： Mou-Shiung Lin

IPC: H01L23/485

CPC classification number: H01L24/05 ,  H01L23/525 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05554 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45169 ,  H01L2224/45173 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48869 ,  H01L2224/48873 ,  H01L2224/49171 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01201 ,  H01L2924/00012 ,  H01L2924/01049

Abstract: A semiconductor chip or wafer comprises a passivation layer and a circuit line. The passivation layer comprises an inorganic layer. The circuit line is over and in touch with the inorganic layer of the passivation layer, wherein the circuit line comprises a first contact point connected to only one second contact point exposed by an opening in the passivation layer, and the positions of the first contact point and the only one second contact point from a top view are different, and the first contact point is used to be wirebonded thereto.

Abstract translation: 半导体芯片或晶片包括钝化层和电路线。 钝化层包括无机层。 电路线与钝化层的无机层结合并接触，其中电路线包括连接到由钝化层中的开口暴露的仅一个第二接触点的第一接触点和第一接触点的位置 并且从俯视图的唯一的一个第二接触点是不同的，并且第一接触点用于与其键合。

公开(公告)号：US06242106B1

公开(公告)日：2001-06-05

申请号：US09305767

申请日：1999-05-05

Applicant: Günter Herklotz ,  Lutz Schräpler ,  Christoph Simons ,  Jürgen Reuel ,  Y. C. Cho

Inventor： Günter Herklotz ,  Lutz Schräpler ,  Christoph Simons ,  Jürgen Reuel ,  Y. C. Cho

IPC: C22C502

CPC classification number: H01L24/45 ,  H01L24/43 ,  H01L2224/4321 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01018 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01038 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01059 ,  H01L2924/0106 ,  H01L2924/01063 ,  H01L2924/01068 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01105 ,  H01L2924/01202 ,  H01L2924/01203 ,  H01L2924/01204 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/30107 ,  Y10T428/12431 ,  H01L2924/01046 ,  H01L2924/01201 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01026 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01062 ,  H01L2924/01064 ,  H01L2924/01065 ,  H01L2924/01066 ,  H01L2924/01067 ,  H01L2924/01069 ,  H01L2924/0107 ,  H01L2924/01071 ,  H01L2924/013 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/00013

Abstract: A fine wire made of an alloy of gold which contains 0.6 to 2 weight % of nickel, or an alloy of gold which contains 0.1 to 2 weight % of nickel, 0.0001 to 0.1 weight % of alkaline earth metal and/or rare earth metal, and optionally 0.1 to 1.0 weight % of platinum and/or palladium . The fine wire is distinguished by a favorable electrical conductivity and a good ratio of strength to elongation. The fine wire is suitable both for wire bonding of semiconductor devices and for producing the ball bumps of flip-chips.

Abstract translation: 由含有0.6〜2重量％镍的金合金或含有0.1〜2重量％的镍的合金，0.0001〜0.1重量％的碱土金属和/或稀土金属制成的细线， 和任选的0.1至1.0重量％的铂和/或钯。 细线通过有利的导电性和良好的强度与伸长率的区别。 细线适用于半导体器件的引线接合和用于制造倒装芯片的球凸块。

公开(公告)号：US20180108631A1

公开(公告)日：2018-04-19

申请号：US15722579

申请日：2017-10-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Toyohiro Aoki ,  Takashi Hisada ,  Eiji Nakamura

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/13 ,  H01L24/742 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/024 ,  H01L2224/0382 ,  H01L2224/03826 ,  H01L2224/03827 ,  H01L2224/0401 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11003 ,  H01L2224/11312 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13018 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/81815 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01201

Abstract: Wafers and methods of forming solder balls include etching a hole in a final redistribution layer over a terminal contact pad on a wafer to expose the terminal contact pad. Solder is injected into the hole using an injection nozzle that is in direct contact with the final redistribution layer. The final redistribution layer is etched back. The injected solder is reflowed to form a solder ball.