公开(公告)号：US20080020603A1

公开(公告)日：2008-01-24

申请号：US11865321

申请日：2007-10-01

Applicant: Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

Inventor： Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

IPC: H01R12/22

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

公开(公告)号：US20080020596A1

公开(公告)日：2008-01-24

申请号：US11865231

申请日：2007-10-01

Applicant: Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

Inventor： Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

Abstract translation: 包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机 还提供了一种制造焊盘栅格阵列中介层结构的方法。

公开(公告)号：US20070298624A1

公开(公告)日：2007-12-27

申请号：US11365366

申请日：2006-03-01

Applicant: Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

Inventor： Gareth Hougham ,  Brian Beaman ,  Evan Colgan ,  Paul Coteus ,  Stefano Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

Abstract translation: 包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机 还提供了一种制造焊盘栅格阵列中介层结构的方法。

公开(公告)号：US07271084B2

公开(公告)日：2007-09-18

申请号：US11330107

申请日：2006-01-12

Applicant: Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

Inventor： Se-young Jeong ,  Nam-seog Kim ,  Oh-se Yong ,  Soon-bum Kim ,  Sun-young Park ,  Ju-hyun Lyu ,  In-young Lee

IPC: H01L21/44 ,  H01L21/461 ,  B23K31/02

CPC classification number: H01L24/13 ,  B23K3/0607 ,  B23K3/0623 ,  H01L21/2885 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/13012 ,  H01L2224/13076 ,  H01L2224/13078 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81141 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09745 ,  H05K2201/10674 ,  H05K2203/048 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusions from the contact pad and the ball pad are sized and arranged to have overlapping upper portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

Abstract translation: 在布置在半导体芯片上的接触焊盘和布置在安装基板上的球垫之间形成加强焊料凸块连接器结构。 半导体芯片包括从中间层的表面向上延伸的至少一个增强突起。 安装基板包括从球垫向上延伸的至少一个加强突起，来自芯片和基板的突起被嵌入在焊料凸块连接器内。 在一些构造中，来自接触垫和球垫的加强突起的尺寸和布置为具有重叠的上部。 这些重叠部分可采取各种各样的构造，其允许突起重叠而不彼此接触，包括针阵列以及周围和被包围的元件的组合。 在每种构造中，加强突起将倾向于抑制裂纹形成和/或裂纹扩展，从而提高可靠性。

公开(公告)号：US07256117B2

公开(公告)日：2007-08-14

申请号：US11614167

申请日：2006-12-21

Applicant: John Paul Tellkamp

Inventor： John Paul Tellkamp

IPC: H01L21/44

CPC classification number: H01L24/83 ,  H01L24/29 ,  H01L24/32 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/0005 ,  H05K3/341 ,  H05K2201/0367 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2201/10969 ,  H05K2203/162 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of reducing a likelihood that a die pad will be delaminated from a die in an integrated circuit die package for a structure design during an attachment of a heat sink member to the die pad using solder, is provided. A sample structure of the structure design is evaluated to determine whether a volume of last solidification for the solder is centrally located with respect to the die pad and is located at or near an interface of the solder and the die pad. If the last solidification volume is centrally located and is located at or near the interface of the solder and the die pad, and if the die pad is delaminated from the die, the structure design is modified so that less metal of the heat sink member is centrally located than before the modifying.

公开(公告)号：US20070128772A1

公开(公告)日：2007-06-07

申请号：US10553076

申请日：2004-04-15

Applicant: Naomi Yonemura ,  Katunori Yashima ,  Yoshihiko Tsujimura ,  Hidenori Ishikura ,  Takashi Saiki

Inventor： Naomi Yonemura ,  Katunori Yashima ,  Yoshihiko Tsujimura ,  Hidenori Ishikura ,  Takashi Saiki

IPC: H01L21/82 ,  H01L23/02

CPC classification number: H01L23/66 ,  H01L21/4857 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/49822 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05666 ,  H01L2224/45111 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/4516 ,  H01L2224/45166 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48472 ,  H01L2224/48611 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48666 ,  H01L2224/48711 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48766 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4886 ,  H01L2224/48866 ,  H01L2224/4911 ,  H01L2224/85411 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85455 ,  H01L2224/8546 ,  H01L2224/85466 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01061 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/19051 ,  H01L2924/30105 ,  H05K1/0224 ,  H05K1/024 ,  H05K1/025 ,  H05K3/0061 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09745 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48811 ,  H01L2224/48824 ,  H01L2224/48744 ,  H01L2224/4876 ,  H01L2224/4866

Abstract: A metal base circuit board to be used for a hybrid integrated circuit, including circuits provided on a metal plate via an insulating layer, a power semiconductor mounted on the circuit, and a control semiconductor to control the power semiconductor, provided on the circuit. A low capacitance portion is embedded under a circuit portion on which the control semiconductor is mounted, preferably. The low capacitance portion is made of a resin containing an inorganic filler and has a dielectric constant of from 2 to 9.

Abstract translation: 用于混合集成电路的金属基底电路板，包括经由绝缘层设置在金属板上的电路，安装在电路上的功率半导体以及控制半导体以控制电路上的功率半导体。 优选地，将低电容部分嵌入在其上安装有控制半导体的电路部分的下方。 低电容部由含有无机填料的树脂构成，介电常数为2〜9。

公开(公告)号：US20070076391A1

公开(公告)日：2007-04-05

申请号：US11163058

申请日：2005-10-04

Applicant: Shih-Ping Hsu

Inventor： Shih-Ping Hsu

IPC: H05K7/06

CPC classification number: H01L23/5389 ,  H01L24/19 ,  H01L24/82 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0203 ,  H05K1/05 ,  H05K1/162 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09554 ,  H05K2201/09745 ,  H01L2224/16225 ,  H01L2924/00

Abstract: A chip embedded packaging structure includes a first metal board, a second metal board having at least a through cavity, in which the second metal board is disposed on the upper surface of the first metal board to form a heat dissipating substrate, at least a semiconductor chip and a capacitor chip embedded in the first metal board and embraced in the through cavity of the second metal board, a passive component layer disposed on part of the upper surface of the second metal board, and at least a build-up circuit layer covering the semiconductor chip, the capacitor chip, and the passive component layer and electrically connecting them through a plurality of conductive vias.

Abstract translation: 芯片嵌入式封装结构包括第一金属板，具有至少一个通孔的第二金属板，其中第二金属板设置在第一金属板的上表面上以形成散热基板，至少半导体 芯片和嵌入在第一金属板中并且包围在第二金属板的通孔中的电容器芯片，设置在第二金属板的上表面的一部分上的无源元件层，以及至少覆盖 半导体芯片，电容器芯片和无源元件层，并通过多个导电通孔将它们电连接。

公开(公告)号：US20070075726A1

公开(公告)日：2007-04-05

申请号：US11607973

申请日：2006-12-04

Applicant: Benson Chan ,  Frank Egitto ,  Voya Markovich

Inventor： Benson Chan ,  Frank Egitto ,  Voya Markovich

IPC: G01R31/26

CPC classification number: G01R1/06711 ,  G01R1/0735 ,  G01R1/07378 ,  H05K1/0393 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09627 ,  H05K2201/09745 ,  H05K2201/10378

Abstract: A test apparatus which uses a pair of substrates and housing to interconnect a host substrate (e.g., PCB) to an electronic device (e.g., semiconductor chip) to accomplish testing of the device. The apparatus includes a housing designed for being positioned on the PCB and have one of the substrates oriented therein during device engagement. The engaging contacts of the upper (second) substrate are sculpted to assure effective chip connection.

Abstract translation: 一种测试装置，其使用一对基板和壳体将主机基板（例如，PCB）与电子设备（例如，半导体芯片）互连以完成设备的测试。 该装置包括被设计用于定位在PCB上的壳体，并且在装置接合期间其中一个基板定向于其中。 上（第二）衬底的接合触点被雕刻以确保有效的芯片连接。

公开(公告)号：US20070063302A1

公开(公告)日：2007-03-22

申请号：US11230772

申请日：2005-09-20

Applicant: Chee Chen ,  Chi Siah ,  Teik Chuan

Inventor： Chee Chen ,  Chi Siah ,  Teik Chuan

IPC: H01L31/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/1184 ,  H01L2224/16 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K3/4007 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/0195 ,  Y02P70/611 ,  H01L2924/00014

Abstract: Some embodiments relate to an electronic assembly that includes a substrate and a plurality of pads. Each of the pads includes a lower section that is embedded in the substrate and a bowl-shaped upper section that is on top of the lower section. The bowl-shaped upper section protrudes from the substrate such that the bowl-shaped upper section is adapted to be soldered to balls or pads on another electronic assembly (e.g., an electronic package that include a die). Other embodiments relate to a method that includes forming a plurality of pads on a substrate such that each of the pads includes a lower section that is embedded in the substrate and an upper section that protrudes from the substrate. The method further includes heating the plurality of pads and engaging a member with the plurality of pads to form the upper section of each pad into a bowl shape.

Abstract translation: 一些实施例涉及包括衬底和多个焊盘的电子组件。 每个焊盘包括嵌入在基板中的下部部分和位于下部部分顶部的碗状上部部分。 碗状上部从基板突出，使得碗状上部适于焊接到另一电子组件（例如，包括模具的电子封装）上的球或焊盘。 其他实施例涉及一种方法，其包括在衬底上形成多个焊盘，使得每个焊盘包括嵌入在衬底中的下部，以及从衬底突出的上部。 该方法还包括加热多个焊盘并使构件与多个焊盘接合，以将每个焊盘的上部部分形成为碗状。

公开(公告)号：US07168154B2

公开(公告)日：2007-01-30

申请号：US10964187

申请日：2004-10-13

Applicant: Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

Inventor： Tatsumi Tsuchiya ,  Yuhsuke Matsumoto ,  Takaaki Murokawa ,  Naoki Fujii ,  Takuya Satoh ,  Yasuhiro Mita ,  Hiroyasu Tsuchida ,  Yoshio Uematsu

IPC: G11B5/127 ,  H04R31/00

CPC classification number: G11B5/4853 ,  G11B5/484 ,  G11B5/486 ,  H01L2224/742 ,  H05K1/189 ,  H05K3/3442 ,  H05K3/3494 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/09745 ,  H05K2203/041 ,  H05K2203/107 ,  H05K2203/159 ,  Y02P70/613 ,  Y10T29/49025 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49046 ,  Y10T29/49144 ,  Y10T29/49179

Abstract: An integrated lead suspension includes a solder ball that is placed between a lead wiring pad provided on a flexure of the suspension, and a bonding pad provided on a slider of a head gimbal section. The lead wiring pad and bonding pad are soldered by melting the solder ball. As a result, there is provided a recessed section into which a solder ball is placed by way of surface raised sections, using gravitational force, in the vicinity of the center line of the surface of the lead wiring pad. In this way the position of the solder ball is not displaced from the center line when a bonding pad and lead wiring pad are connected by means of a solder ball.

Abstract translation: 一体化引线悬架包括放置在设置在悬架的弯曲部上的引线布线焊盘之间的焊球和设置在头部万向节部分的滑块上的焊盘。 引线接线板和接合焊盘通过熔化焊球进行焊接。 结果，在引线布线焊盘的表面的中心线附近，使用重力提供了通过表面凸起部分放置焊球的凹部。 以这种方式，当通过焊球连接接合焊盘和引线接线焊盘时，焊球的位置不会偏离中心线。