公开(公告)号：US06467161B2

公开(公告)日：2002-10-22

申请号：US09812989

申请日：2001-03-20

Applicant: Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

Inventor： Achyuta Achari ,  Brenda Joyce Nation ,  Delin Li ,  Lakhi N. Goenka ,  Richard Keith McMillan ,  Vivek A. Jairazbhoy

IPC: H05K320

CPC classification number: H05K3/4685 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10, 110 for making multi-layer electronic circuit boards 82, 148 having metallized apertures 18, 20, 118, 120 which may be selectively and electrically connected to a source of ground potential.

Abstract translation: 一种用于制造具有金属化孔18,20,118,120的多层电子电路板82,148的方法10,110，其可以选择性地和电连接到地电位源。

公开(公告)号：US20020079577A1

公开(公告)日：2002-06-27

申请号：US10086223

申请日：2002-03-01

Inventor： Tony H. Ho

IPC: H01L023/48 ,  H01L023/52 ,  H01L029/40

CPC classification number: H01L24/81 ,  H01L23/49816 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2201/094 ,  H05K2201/2036 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention discloses a semiconductor package that forms a solder array joints on the die surface and their corresponding PCB respectively. The life times of array solders are increased through use of two set of array joints that have high and low melting points. The high melting solders are served as the dummy ones to sustain the overall stand-offs of array joints. The solder size in the same solder array is identical. The melting solders with high and low melting points implemented on a semiconductor die are heading one to one attached to thecorrespondingly melting solders of high and low melting points in PCB site. The reflow temperature of smt assembly is between the aforemetioned high and low melting points. In addition, the solder joints with directional properties are made so as to make the fanout connections on PCB site.

Abstract translation: 本发明公开了一种半导体封装，其分别在芯片表面上形成焊料阵列接头及其对应的PCB。 通过使用具有高低熔点的两组阵列接头来增加阵列焊料的使用寿命。 高熔点焊料用作虚拟焊料，以维持阵列接头的整体支座。 相同焊料阵列中的焊料尺寸相同。 在半导体芯片上实现的具有高熔点和低熔点的熔融焊料是一个一个连接到PCB站点中相应熔融的高熔点和低熔点焊料的焊料。 smt装配的回流温度介于上述高低熔点之间。 此外，具有定向性能的焊点可以在PCB位置进行扇出连接。

公开(公告)号：US06400234B1

公开(公告)日：2002-06-04

申请号：US09500995

申请日：2000-02-09

Applicant: Hideyuki Ohhashi ,  Yukihiro Tahara ,  Moriyasu Miyazaki

Inventor： Hideyuki Ohhashi ,  Yukihiro Tahara ,  Moriyasu Miyazaki

IPC: H01P502

CPC classification number: H01P3/088 ,  H01P5/085 ,  H01R12/523 ,  H05K1/0222 ,  H05K1/0251 ,  H05K1/0272 ,  H05K3/0061 ,  H05K3/429 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09745 ,  H05K2201/09809 ,  H05K2201/10356

Abstract: A reflection characteristic in a high frequency region at a feeding point into a strip line is improved and the assembly of a strip line feeding apparatus facilitated by the method and apparatus herein. The strip line includes a strip line pattern on a surface of a first dielectric substrate having a ground conductor pattern disposed on the opposite surface thereof, and a second ground conductor pattern disposed on a surface of a second dielectric substrate. A serial high impedance portion is disposed at an area near the tip portion of the strip line pattern. The high impedance portion includes a portion of the strip line pattern having narrowed width or a hole disposed under a through-hole for an inner conductor, which electrically connects the strip line pattern and an inner conductor. Dimensions of the high impedance portion are controlled to cancel out parasitic susceptance due to the discontinuous structure. A matching through-hole is further disposed in the second dielectric substrate in an area separated from the tip portion of the strip line pattern by a distance of around 25% of the typical wave length. The matching through-hole is elongated to a land pattern in a hole disposed in the second ground conductor pattern so as to electrically connect the conductor strip pattern and the land pattern.

Abstract translation: 提高了进入带状线的馈电点的高频区域的反射特性，并且通过本文的方法和装置促进了带状线馈电装置的组装。 带状线包括在第一电介质基板的表面上的带状线图案，该第一电介质基板的表面上设置有设置在其相对表面上的接地导体图案，以及设置在第二电介质基板的表面上的第二接地导体图案。 串联高阻抗部分设置在带状线图案的尖端部分附近的区域。 高阻抗部分包括具有变窄的宽度的带状线图案的一部分或设置在用于内导体的通孔下方的孔，其将带状线图案和内导体电连接。 控制高阻抗部分的尺寸以抵消由于不连续结构引起的寄生电容。 在第二电介质基板中，与带状线图案的前端部分隔开约25％的典型波长的距离的区域，进一步配置匹配的通孔。 匹配的通孔被延伸到设置在第二接地导体图案中的孔中的焊盘图案，以便电连接导体带图案和焊盘图案。

公开(公告)号：US20020025599A1

公开(公告)日：2002-02-28

申请号：US09941384

申请日：2001-08-28

Applicant: Aptos Corporation

Inventor： Chung W. Ho ,  Tsing-Chow Wang

IPC: H01L021/48

CPC classification number: H01L24/12 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13583 ,  H01L2224/136 ,  H01L2224/13647 ,  H01L2224/13671 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01054 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/1025 ,  H05K2201/2081 ,  H05K2203/0315 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Within a method for forming a solder interconnection structure for use within a microelectronic fabrication, there is first provided a substrate having formed thereover a bond pad. There is then formed upon the bond pad a first solder interconnection layer. There is then formed over the first solder interconnection layer an annular solder non-wettable copper oxide layer which does not cover an upper dome portion of the first solder interconnection layer. There is then formed over the upper dome portion of the first solder interconnection layer and not upon the annular solder non-wettable copper oxide layer a second solder interconnection layer.

Abstract translation: 在用于形成在微电子制造中使用的焊料互连结构的方法中，首先提供了在接合焊盘之上形成的衬底。 然后在接合焊盘上形成第一焊料互连层。 然后在第一焊料互连层上形成不覆盖第一焊料互连层的上部圆顶部分的环形焊料不可湿性氧化铜层。 然后形成在第一焊料互连层的上部圆顶部分上方，而不是在环形焊料不可湿性氧化铜层上形成第二焊料互连层。

公开(公告)号：US06350668B1

公开(公告)日：2002-02-26

申请号：US09688067

申请日：2000-10-13

Applicant: Kishore K. Chakravorty

Inventor： Kishore K. Chakravorty

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/05616 ,  H01L2224/05644 ,  H01L2224/06505 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/14505 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A first plurality of metal bumps is formed on a semiconductor wafer containing a plurality of chips, each of the first plurality of bumps being in electrical contact with a contact pad on one of the chips. An encapsulant layer is deposited over the first plurality of metal bumps and then polished to expose a top surface on each of the metal bumps. A second plurality of metal bumps is formed on the exposed top surfaces of the first plurality of plurality of bumps, respectively. The wafer is then sawed to separate the individual chips, yielding semiconductor packages which have the same lateral dimensions as the chips. Alternatively, to facilitate the encapsulation process, the wafer can be sawed into rectangular, multi-chip segments before the encapsulant layer is deposited. After the encapsulant layer has been applied and polished and the second plurality of conductive bumps have been formed, the segments are then separated into individual chips. The first plurality of metal bumps can be deposited directly on the contact pads, with or without an underbump metalization layer, or on metal conductive traces over one or more dielectric layers.

Abstract translation: 在包含多个芯片的半导体晶片上形成第一多个金属凸块，所述第一多个凸块中的每一个与所述芯片之一上的接触焊盘电接触。 在第一多个金属凸块上沉积密封剂层，然后抛光以暴露每个金属凸块上的顶表面。 第二多个金属凸块分别形成在第一多个凸块的暴露的顶表面上。 然后锯切晶片以分离各个芯片，产生具有与芯片相同的横向尺寸的半导体封装。 或者，为了便于封装工艺，可以在沉积密封剂层之前将晶片锯成矩形的多芯片片段。 在施加和抛光密封剂层并形成第二多个导电凸块之后，将这些段分离成单独的芯片。 第一多个金属凸块可以直接沉积在具有或不具有底部凹凸金属化层的接触焊盘上，或者在一个或多个电介质层上的金属导电迹线上。

公开(公告)号：US20020013071A1

公开(公告)日：2002-01-31

申请号：US09753737

申请日：2001-01-02

Inventor： E. C. Ong

IPC: H05K001/00

CPC classification number: H05K3/3436 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/1191 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/274 ,  H01L2224/45144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2203/025 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method for final testing die on a wafer is provided wherein wafers having die are first enhanced by adding contact extensions to contact pads of the die, adding a protective polymer layer covering the contact extensions and planarizing the polymer layer to expose the contact extensions. After this enhancement final testing may be done by probe in the wafer form.

Abstract translation: 提供了一种用于在晶片上进行最终测试的方法，其中通过向模具的接触焊盘添加接触延伸来首先增强具有管芯的晶片，添加覆盖接触延伸部并平坦化聚合物层以暴露接触延伸部的保护性聚合物层。 在该增强之后，可以通过在晶片形式中探测来完成最终测试。

公开(公告)号：US06342443B1

公开(公告)日：2002-01-29

申请号：US09346735

申请日：1999-07-02

Applicant: Su Tao ,  Wei-Chung Wang ,  Jen-Kuang Fang

Inventor： Su Tao ,  Wei-Chung Wang ,  Jen-Kuang Fang

IPC: H01L2144

CPC classification number: H01L24/14 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/1184 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/81211 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/013 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A packaging process providing a die with C4 solder bumps and a polymer substrate first. It then jets the melted second solder onto each of the C4 solder bumps forming a second solder bump. After reflowing and leveling the solder bumps, the die is flipped and combined with the substrate. Then heat treatment proceeds with the combination of the die and the substrate forming a flip chip package with collapse-controlled solder bump on the polymer substrate.

Abstract translation: 首先提供具有C4焊料凸块的模具和聚合物基板的封装工艺。 然后将熔化的第二焊料喷射到形成第二焊料凸块的每个C4焊料凸块上。 在回流和调平焊料凸块之后，将模具翻转并与基板组合。 然后热处理随着管芯和衬底的组合进行，在聚合物衬底上形成具有塌陷控制的焊料凸块的倒装芯片封装。

公开(公告)号：US20010037898A1

公开(公告)日：2001-11-08

申请号：US09815234

申请日：2001-03-22

Inventor： Bharat Z. Patel ,  Jay D. Baker ,  Mohan R. Paruchuri

IPC: H05K001/11

CPC classification number: H05K3/462 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49153 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method 10, 90 for making a multi-layer electronic circuit board 82, 168 including the steps of forming at least one protuberance 15, 100 upon an electrically conductive member 12, 92 and adding additional electrically conductive layers of material 34, 56, 58, 104, 114, 138, 140 to the member 12, 92 while selectively extending the protuberance 15, 100 within the layers 82, 168, thereby forming a circuit board 82, 168. A portion of the formed circuit board may be etched in order to selectively create air-bridges 86 or interconnection portions 164.

Abstract translation: 一种用于制造多层电子电路板82,168的方法10,90，包括在导电构件12,92上形成至少一个突起15,100的步骤，并且添加另外的材料34,56,58的导电层 ，104,114,138,140连接到构件12,92，同时在层82,168内选择性地延伸突起15,100，从而形成电路板82,168。形成的电路板的一部分可以按顺序蚀刻 以选择性地产生空气桥86或互连部分164。

公开(公告)号：US6127735A

公开(公告)日：2000-10-03

申请号：US710992

申请日：1996-09-25

Applicant: Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

Inventor： Daniel George Berger ,  Guy Paul Brouillette ,  David Hirsch Danovitch ,  Peter Alfred Gruber ,  Bruce Lee Humphrey ,  Michael Liehr ,  William Thomas Motsiff ,  Carlos Juan Sambucetti

IPC: B23K35/26 ,  H01L21/60 ,  H05K3/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H05K3/3436 ,  H05K3/3468 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11003 ,  H01L2224/11822 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13609 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H05K2201/0379 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/128 ,  H05K3/3463 ,  H05K3/3478 ,  Y02P70/613

Abstract: A method of forming interconnects on an electronic device that can be bonded to another electronic device at a low processing temperature can be carried out by depositing a first interconnect material on the electronic device forming protrusions and then depositing a second interconnect material to at least partially cover the protrusions, wherein the second interconnect material has a lower flow temperature than the first interconnect material. The method is carried out by flowing a molten solder into a mold having microcavities to fill the cavities and then allowed to solidify. The mold is then aligned with a silicon wafer containing chips deposited with high melting temperatures solder bumps such that each microcavity of the mold is aligned with each high melting temperature solder bump on the chip. The aligned mold/wafer assembly is then passed through a reflow furnace to effect the transfer of the low melting temperature solder in the mold cavities onto the tip of the high melting temperature solder bumps on the wafer. A dual metallurgical composition bump is thereby formed by the two different solder alloys.

Abstract translation: 可以在能够以低处理温度结合到另一电子设备的电子设备上形成互连的方法可以通过在形成突起的电子设备上沉积第一互连材料，然后沉积第二互连材料至少部分覆盖 所述突起，其中所述第二互连材料具有比所述第一互连材料低的流动温度。 该方法通过将熔融焊料流入具有微腔的模具中以填充空腔，然后使其固化来进行。 然后将模具与包含沉积有高熔点温度焊料凸块的芯片的硅晶片对准，使得模具的每个微腔与芯片上的每个高熔点温度焊料凸块对准。 然后将对准的模具/晶片组件通过回流炉，以将模腔中的低熔点焊料转移到晶片上的高熔点温度焊料凸块的尖端上。 由此由两种不同的焊料合金形成双金属组合物凸块。

公开(公告)号：US5909009A

公开(公告)日：1999-06-01

申请号：US662005

申请日：1996-06-12

Applicant: Shinji Tanaka

Inventor： Shinji Tanaka

IPC: H01L21/68 ,  H01L23/538 ,  H05K1/09 ,  H05K3/00 ,  H05K3/46 ,  H05K1/14

CPC classification number: H01L21/6835 ,  H01L23/5385 ,  H05K3/4614 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2924/0002 ,  H05K1/095 ,  H05K2201/0379 ,  H05K2201/09809 ,  H05K2203/016 ,  H05K2203/061 ,  H05K3/007 ,  H05K3/4641

Abstract: A laminate organic resin wiring board and a method of producing the same are disclosed. The wiring board has a plurality of subassemblies each having a conductive resin layer serving as a ground or feed layer on its top. The subassemblies are adhered to each other at their conductive resin layers. This successfully eliminates the need for an organic resin layer for insulation customarily formed on the top of the individual subassembly. The decrease in the number of layers reduces the period of time necessary for the production of the wiring board.

Abstract translation: 公开了一种层压有机树脂布线板及其制造方法。 布线板具有多个子组件，每个子组件的顶部具有用作接地或馈电层的导电树脂层。 子组件在其导电树脂层彼此粘合。 这成功地消除了在各个子组件的顶部通常形成的用于绝缘的有机树脂层的需要。 层数的减少减少了生产布线板所需的时间。