公开(公告)号：US20120112201A1

公开(公告)日：2012-05-10

申请号：US12942437

申请日：2010-11-09

申请人： Takukazu OTSUKA ,  Keiji OKUMURA ,  Brian LYNN ROWDEN

发明人： Takukazu OTSUKA ,  Keiji OKUMURA ,  Brian LYNN ROWDEN

IPC分类号： H01L23/498 ,  B32B15/01 ,  B23K1/20 ,  H01L29/02 ,  H01L23/492

CPC分类号： B32B15/018 ,  B23K1/0016 ,  B23K35/0238 ,  B23K35/262 ,  B23K35/3006 ,  B23K2101/40 ,  H01L23/053 ,  H01L23/3735 ,  H01L23/488 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/271 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29155 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48229 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83204 ,  H01L2224/83211 ,  H01L2224/83801 ,  H01L2224/83825 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/3841 ,  Y10T428/12708 ,  H01L2924/01047 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A high melting point soldering layer includes a low melting point metal layer, a first high melting point metal layer disposed on a surface of the low melting point metal layer, and a second high melting point metal layer disposed at a back side of the low melting point metal layer. The low melting point metal layer, the first high melting point metal layer, and the second high melting point metal layer are mutually alloyed by transient liquid phase bonding, by annealing not less than a melting temperature of the low melting point metal layer, diffusing the metal of the low melting point metal layer into an alloy of the first high melting point metal layer and the second high melting point metal layer. The high melting point soldering layer has a higher melting point temperature than that of the low melting point metal layer. It is provided a binary based high melting point soldering layer having TLP bonding of a high melting point according to a low temperature processing, a fabrication method for the high melting point soldering layer and a semiconductor device to which the high melting point soldering layer is applied.

摘要翻译： 高熔点焊接层包括低熔点金属层，设置在低熔点金属层的表面上的第一高熔点金属层和设置在低熔点金属层的背面的第二高熔点金属层 点金属层。 低熔点金属层，第一高熔点金属层和第二高熔点金属层通过瞬态液相结合相互合金化，通过退火不低于低熔点金属层的熔融温度，将 低熔点金属层的金属成为第一高熔点金属层和第二高熔点金属层的合金。 高熔点焊接层的熔点温度高于低熔点金属层。 提供了一种基于低温处理的具有高熔点TLP键合的二元基高熔点焊接层，用于高熔点焊接层的制造方法和施加高熔点焊接层的半导体器件 。

公开(公告)号：US20120068325A1

公开(公告)日：2012-03-22

申请号：US13273389

申请日：2011-10-14

申请人： Ruben B. Montez ,  Alex P. Pamatat

发明人： Ruben B. Montez ,  Alex P. Pamatat

IPC分类号： H01L21/50 ,  H01L23/12

CPC分类号： H01L23/10 ,  B81B2207/097 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L21/50 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02 ,  H01L2224/022 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05638 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2746 ,  H01L2224/276 ,  H01L2224/29013 ,  H01L2224/29016 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29117 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83457 ,  H01L2224/83466 ,  H01L2224/83469 ,  H01L2224/83481 ,  H01L2224/83484 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/10157 ,  H01L2924/15159 ,  H01L2924/164 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

摘要： In one embodiment, a semiconductor structure including a first substrate, a semiconductor device on the first substrate, a second substrate, and a conductive bond between the first substrate and the second substrate that surrounds the semiconductor device to seal the semiconductor device between the first substrate and the second substrate. The conductive bond comprises metal, silicon, and germanium. A percentage by atomic weight of silicon in the conductive bond is greater than 5%.

摘要翻译： 在一个实施例中，包括第一衬底，第一衬底上的半导体器件，第二衬底和围绕半导体器件的第一衬底和第二衬底之间的导电结合的半导体结构，以密封半导体器件在第一衬底 和第二基板。 导电键包括金属，硅和锗。 导电键中硅的原子量的百分比大于5％。

公开(公告)号：US08058143B2

公开(公告)日：2011-11-15

申请号：US12356939

申请日：2009-01-21

申请人： Ruben B. Montez ,  Alex P. Pamatat

发明人： Ruben B. Montez ,  Alex P. Pamatat

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L23/10 ,  B81B2207/097 ,  B81C1/00269 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L21/50 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02 ,  H01L2224/022 ,  H01L2224/036 ,  H01L2224/0391 ,  H01L2224/04026 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05638 ,  H01L2224/2745 ,  H01L2224/27452 ,  H01L2224/2746 ,  H01L2224/276 ,  H01L2224/29013 ,  H01L2224/29016 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29117 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32502 ,  H01L2224/32506 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83411 ,  H01L2224/83424 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83457 ,  H01L2224/83466 ,  H01L2224/83469 ,  H01L2224/83481 ,  H01L2224/83484 ,  H01L2224/83805 ,  H01L2224/94 ,  H01L2924/10157 ,  H01L2924/15159 ,  H01L2924/164 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83

摘要： A method that in one embodiment is useful in bonding a first substrate to a second substrate includes forming a layer including metal over the first substrate. The layer including metal in one embodiment surrounds a semiconductor device, which can be a micro electromechanical system (MEMS) device. On the second substrate is formed a first layer comprising silicon. A second layer comprising germanium and silicon is formed on the first layer. A third layer comprising germanium is formed on the second layer. The third layer is brought into contact with the layer including metal. Heat (and pressure in some embodiments) is applied to the third layer and the layer including metal to form a mechanical bond material between the first substrate and the second substrate in which the mechanical bond material is electrically conductive. In the case of the mechanical bond surrounding a semiconductor device such as a MEMS, the mechanical bond can be particularly advantageous as a hermetic seal for protecting the MEMS.

摘要翻译： 在一个实施方案中用于将第一衬底粘合到第二衬底的方法包括在第一衬底上形成包括金属的层。 在一个实施例中包括金属的层围绕半导体器件，其可以是微机电系统（MEMS）器件。 在第二基板上形成包含硅的第一层。 在第一层上形成包括锗和硅的第二层。 在第二层上形成包含锗的第三层。 第三层与包括金属的层接触。 在第三层和包含金属的层上施加热（和一些实施例中的压力）以在第一基板和第二基板之间形成机械接合材料，其中机械接合材料是导电的。 在诸如MEMS之类的半导体器件周围的机械接合的情况下，作为用于保护MEMS的气密密封件，机械结合可能是特别有利的。

公开(公告)号：US08034662B2

公开(公告)日：2011-10-11

申请号：US12406271

申请日：2009-03-18

申请人： Maxat Touzelbaev ,  Gamal Refai-Ahmed ,  Yizhang Yang ,  Bryan Black

发明人： Maxat Touzelbaev ,  Gamal Refai-Ahmed ,  Yizhang Yang ,  Bryan Black

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/42 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/29076 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29169 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/013 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

摘要翻译： 公开了各种半导体芯片热界面材料的方法和装置。 一方面，提供了一种在第一半导体芯片和散热器之间建立热接触的方法。 该方法包括将包含支撑结构的热界面材料层放置在第一半导体芯片上。 散热器位于热界面材料层附近。 热界面材料层被回流以与第一半导体芯片和散热器两者建立热接触。

公开(公告)号：US20110193231A1

公开(公告)日：2011-08-11

申请号：US12885233

申请日：2010-09-17

申请人： Peter ELENIUS ,  Deok Hoon KIM ,  Young Sang CHO

发明人： Peter ELENIUS ,  Deok Hoon KIM ,  Young Sang CHO

IPC分类号： H01L23/488 ,  H01L21/768

CPC分类号： H01L23/10 ,  H01L23/3128 ,  H01L23/564 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14683 ,  H01L31/0203 ,  H01L2224/13 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13147 ,  H01L2224/14155 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/29011 ,  H01L2224/29014 ,  H01L2224/29035 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32 ,  H01L2224/32227 ,  H01L2224/32503 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/83 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83447 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/9211 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15321 ,  H01L2924/15788 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronic device package includes a substrate assembly, an electronic device disposed to face the substrate assembly, and a sealing ring or rings including a sealing layer and a bonding layer that is disposed between the substrate assembly and the electronic device, wherein the sealing ring(s) has a closed loop shape surrounding a sealing region of the electronic device, and the bonding layer is formed through a reaction of the sealing layer and sealing layer pad with a low-melting-point material layer whose melting point is lower than that of the sealing layer and sealing ring pad. The bonding layer is formed of an intermetallic compound of the sealing layer, sealing ring pad and low-melting-point material that melts at a temperature greater than the melting temperature of the low-melting-point material. The device package also includes electrical connections in the form of joints between the substrate assembly and electronic device.

摘要翻译： 电子器件封装包括衬底组件，设置为面对衬底组件的电子器件，以及密封环或环，其包括设置在衬底组件和电子器件之间的密封层和接合层，其中密封环 s）具有围绕电子器件的密封区域的闭环形状，并且通过密封层和密封层焊盘与熔点低于熔点的低熔点材料层的反应形成接合层 密封层和密封环垫。 接合层由密封层，密封环垫和低熔点材料的金属间化合物形成，其熔点高于低熔点材料的熔融温度。 器件封装还包括在衬底组件和电子器件之间的接合形式的电连接。

公开(公告)号：US20110081738A1

公开(公告)日：2011-04-07

申请号：US12926743

申请日：2010-12-07

申请人： Mitsuhiko Ogihara ,  Hiroyuki Fujiwara ,  Takahito Suzuki ,  Masaaki Sakuta ,  Ichimatsu Abiko

发明人： Mitsuhiko Ogihara ,  Hiroyuki Fujiwara ,  Takahito Suzuki ,  Masaaki Sakuta ,  Ichimatsu Abiko

IPC分类号： H01L21/44 ,  H01L33/08

CPC分类号： H01L24/83 ,  B41J2/45 ,  H01L24/29 ,  H01L24/32 ,  H01L27/153 ,  H01L2224/27444 ,  H01L2224/2747 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29114 ,  H01L2224/29117 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/32502 ,  H01L2224/83005 ,  H01L2224/83011 ,  H01L2224/83013 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/8382 ,  H01L2224/83825 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/10349 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00

摘要： A semiconductor composite apparatus includes a semiconductor thin film layer and a substrate. The semiconductor thin film layer and the substrate are bonded to each other with a layer of an alloy of a high-melting-point metal and a low-melting-point metal formed between the semiconductor thin film layer and the substrate. The alloy has a higher melting point than the low-melting-point metal. The layer of the alloy contains a product resulting from a reaction of the low-melting-point metal and a material of said semiconductor thin film layer.

摘要翻译： 半导体复合装置包括半导体薄膜层和基板。 半导体薄膜层和基板通过形成在半导体薄膜层和基板之间的高熔点金属和低熔点金属的合金层彼此接合。 该合金的熔点高于低熔点金属。 该合金层含有由低熔点金属与所述半导体薄膜层的材料反应产生的产物。

公开(公告)号：US20080017987A1

公开(公告)日：2008-01-24

申请号：US11890965

申请日：2007-08-08

申请人： Sven Fuchs ,  Mark Pavier

发明人： Sven Fuchs ,  Mark Pavier

IPC分类号： H01L23/482

CPC分类号： H01L24/30 ,  H01L23/3107 ,  H01L23/498 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2908 ,  H01L2224/29124 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/30505 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73153 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0483 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/13033 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/3651 ,  H01L2924/00

摘要： A semiconductor device that includes an electrode of one material and a conductive material of lower resistivity formed over the electrode and a process for fabricating the semiconductor device.

摘要翻译： 一种半导体器件，其包括在电极上形成的一种材料的电极和具有较低电阻率的导电材料，以及制造该半导体器件的工艺。

公开(公告)号：US07193239B2

公开(公告)日：2007-03-20

申请号：US10614067

申请日：2003-07-03

申请人： Glenn J Leedy

发明人： Glenn J Leedy

IPC分类号： H01L29/04 ,  H01L23/02

CPC分类号： H01L27/10897 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C29/44 ,  G11C29/81 ,  G11C29/846 ,  G11C29/848 ,  H01L23/481 ,  H01L25/18 ,  H01L27/0688 ,  H01L27/105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L2924/01079 ,  Y10S438/977 ,  H01L2924/00014

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 μm in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路薄化到小于50um的厚度，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。

公开(公告)号：US20060131712A1

公开(公告)日：2006-06-22

申请号：US11291072

申请日：2005-12-01

申请人： Simon Jerebic ,  Jens Pohl ,  Horst Theuss

发明人： Simon Jerebic ,  Jens Pohl ,  Horst Theuss

IPC分类号： H01L23/06

CPC分类号： H01L24/71 ,  H01L23/4827 ,  H01L23/562 ,  H01L23/564 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05599 ,  H01L2224/274 ,  H01L2224/278 ,  H01L2224/29138 ,  H01L2224/29155 ,  H01L2224/29157 ,  H01L2224/2916 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75733 ,  H01L2224/83121 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/839 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/95144 ,  H01L2924/00014 ,  H01L2924/0101 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01064 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/85399 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/27 ,  H01L2924/00012

摘要： An electronic component includes a semiconductor chip with a chip topside, an integrated circuit, and a chip backside. The chip backside includes a magnetic layer. The electronic component further includes a chip carrier with a magnetic layer on its carrier topside. At least one of the two magnetic layers is permanently magnetic such that the semiconductor chip is magnetically fixed on the chip carrier.

摘要翻译： 电子部件包括具有芯片顶侧的半导体芯片，集成电路和芯片背面。 芯片背面包括磁性层。 电子部件还包括其载体顶侧上具有磁性层的芯片载体。 两个磁性层中的至少一个是永久磁性的，使得半导体芯片被磁性地固定在芯片载体上。

公开(公告)号：US6133640A

公开(公告)日：2000-10-17

申请号：US971565

申请日：1997-11-17

申请人： Glenn J. Leedy

发明人： Glenn J. Leedy

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C5/04 ,  H01L21/768 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L27/06 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78 ,  H01L33/00

CPC分类号： H01L27/10897 ,  G11C29/846 ,  G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/105 ,  G11C29/44 ,  G11C29/81 ,  G11C29/848 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29124 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29166 ,  H01L2224/29169 ,  H01L2224/8083 ,  H01L2225/06541 ,  H01L25/18 ,  H01L2924/01079 ,  Y10S438/977

摘要： A Three-Dimensional Structure (3DS) Memory allows for physical separation of the memory circuits and the control logic circuit onto different layers such that each layer may be separately optimized. One control logic circuit suffices for several memory circuits, reducing cost. Fabrication of 3DS memory involves thinning of the memory circuit to less than 50 .mu.m in thickness and bonding the circuit to a circuit stack while still in wafer substrate form. Fine-grain high density inter-layer vertical bus connections are used. The 3DS memory manufacturing method enables several performance and physical size efficiencies, and is implemented with established semiconductor processing techniques.

摘要翻译： 三维结构（3DS）存储器允许将存储器电路和控制逻辑电路物理分离到不同的层上，使得每个层可以被单独优化。 一个控制逻辑电路足以用于多个存储器电路，从而降低成本。 3DS存储器的制造涉及将存储器电路薄化到厚度小于50微米，并将电路结合到电路堆栈同时仍然是晶片衬底形式。 使用细粒度高密度层间垂直总线连接。 3DS存储器制造方法可实现多种性能和物理尺寸效率，并采用已建立的半导体处理技术实现。