公开(公告)号：US10115672B2

公开(公告)日：2018-10-30

申请号：US15816743

申请日：2017-11-17

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Il Kwon Shim ,  Pandi C. Marimuthu ,  Yaojian Lin

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/48 ,  H01L25/16

Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

公开(公告)号：US20180158779A1

公开(公告)日：2018-06-07

申请号：US15807833

申请日：2017-11-09

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： DeokKyung Yang ,  Woonjae Beak ,  YiSu Park ,  OhHan Kim ,  HunTeak Lee ,  HeeSoo Lee

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/552 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor device has a substrate with a first opening and second opening formed in the substrate. A first semiconductor component is disposed on the substrate. The substrate is disposed on a carrier. A second semiconductor component is disposed on the carrier in the first opening of the substrate. A third semiconductor component is disposed in the second opening. The third semiconductor component is a semiconductor package in some embodiments. A first shielding layer may be formed over the semiconductor package. An encapsulant is deposited over the substrate, first semiconductor component, and second semiconductor component. A shielding layer may be formed over the encapsulant.

公开(公告)号：US09978654B2

公开(公告)日：2018-05-22

申请号：US13832449

申请日：2013-03-15

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Kang Chen

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/66 ,  H01L21/56 ,  H01L23/498 ,  H01L23/28 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L21/78 ,  H01L23/538

CPC classification number: H01L22/32 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/565 ,  H01L21/78 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92125 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a substrate including first and second conductive layers formed over first and second opposing surfaces of the substrate. A plurality of wire studs or stud bumps is formed over the substrate. A semiconductor die is mounted to the substrate between the wire studs. A first encapsulant is deposited around the semiconductor die. A first interconnect structure is formed over the semiconductor die and first encapsulant. A second encapsulant is deposited over the substrate, semiconductor die, and first interconnect structure. The second encapsulant can be formed over a portion of the semiconductor die and side surface of the substrate. A portion of the second encapsulant is removed to expose the substrate and first interconnect structure. A second interconnect structure is formed over the second encapsulant and first interconnect structure and electrically coupled to the wire studs. A discrete semiconductor device can be formed on the interconnect structure.

公开(公告)号：US20180108542A1

公开(公告)日：2018-04-19

申请号：US15846014

申请日：2017-12-18

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Reza A. Pagaila ,  Yaojian Lin ,  Jun Mo Koo ,  HeeJo Chi

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48157 ,  H01L2224/48158 ,  H01L2224/4816 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81001 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor device has an interposer mounted over a carrier. The interposer includes TSV formed either prior to or after mounting to the carrier. An opening is formed in the interposer. The interposer can have two-level stepped portions with a first vertical conduction path through a first stepped portion and second vertical conduction path through a second stepped portion. A first and second semiconductor die are mounted over the interposer. The second die is disposed within the opening of the interposer. A discrete semiconductor component can be mounted over the interposer. A conductive via can be formed through the second die or encapsulant. An encapsulant is deposited over the first and second die and interposer. A portion of the interposer can be removed to that the encapsulant forms around a side of the semiconductor device. An interconnect structure is formed over the interposer and second die.

公开(公告)号：US09922915B2

公开(公告)日：2018-03-20

申请号：US13965356

申请日：2013-08-13

Applicant: STATS ChipPAC, Ltd.

Inventor： Rajendra D. Pendse

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L23/498 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L21/76885 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13111 ,  H01L2224/1607 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75301 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. [The fusible portion melts at a temperature which avoids damage to the substrate during reflow.] The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.

公开(公告)号：US20180061806A1

公开(公告)日：2018-03-01

申请号：US15686584

申请日：2017-08-25

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： JinHee Jung ,  OhHan Kim ,  InSang Yoon

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L24/96 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49838 ,  H01L23/49861 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/95001 ,  H01L2224/95136 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A semiconductor device has a carrier with an adhesive layer formed over the carrier. Alignment marks are provided for picking and placing the electrical component on the carrier or adhesive layer. An electrical component is disposed on the adhesive layer by pressing terminals of the electrical component into the adhesive layer. The electrical component can be a semiconductor die, discrete component, electronic module, and semiconductor package. A leadframe is disposed over the adhesive layer. A shielding layer is formed over the electrical component. An encapsulant is deposited over the electrical component. The carrier and adhesive layer are removed so that the terminals of the electrical component extend out from the encapsulant for electrical interconnect. A substrate includes a plurality of conductive traces. The semiconductor device is disposed on the substrate with the terminals of the electrical component in contact with the conductive traces.

公开(公告)号：US09905491B1

公开(公告)日：2018-02-27

申请号：US14039938

申请日：2013-09-27

Applicant: In Sang Yoon ,  DeokKyung Yang ,  SeongHun Mun

Inventor： In Sang Yoon ,  DeokKyung Yang ,  SeongHun Mun

IPC: H01L21/50 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L23/3128

Abstract: Semiconductor packages with multiple substrates can incorporate cavities in a portion of an upper substrate to minimize or reduce void formations during a molding process. The cavities can be formed substantially over the integrated circuit devices and not over the internal interconnects to further facilitate the flow of the molding compound. The combination with extension members or recesses on a top or exterior surface of the upper substrate can further cut down on bleeding or spill over of the molding compound between adjacent packages and improve device reliability and yield.

公开(公告)号：US09865525B2

公开(公告)日：2018-01-09

申请号：US14326789

申请日：2014-07-09

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Yu Gu

IPC: H01L21/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/48 ,  H01L23/13 ,  H01L23/00 ,  H01L21/56 ,  H01L23/28 ,  H01L23/498

CPC classification number: H01L23/481 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/568 ,  H01L23/13 ,  H01L23/28 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24195 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/81805 ,  H01L2924/00012

Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.

公开(公告)号：US09865524B2

公开(公告)日：2018-01-09

申请号：US14222547

申请日：2014-03-21

Applicant: STATS ChipPAC, Ltd.

Inventor： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/66

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

公开(公告)号：US09842808B2

公开(公告)日：2017-12-12

申请号：US13645385

申请日：2012-10-04

Applicant: STATS ChipPAC, Ltd.

Inventor： HanGil Shin ,  NamJu Cho ,  HeeJo Chi

IPC: H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/495 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/215 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of semiconductor die or components mounted over a carrier. A leadframe is mounted over the carrier between the semiconductor die. The leadframe has a plate and bodies extending from the plate. The bodies of the leadframe are disposed around a perimeter of the semiconductor die. An encapsulant is deposited over the carrier, leadframe, and semiconductor die. A plurality of conductive vias is formed through the encapsulant and electrically connected to the bodies of the leadframe and contact pads on the semiconductor die. An interconnect structure is formed over the encapsulant and electrically connected to the conductive vias. A first channel is formed through the interconnect structure, encapsulant, leadframe, and partially through the carrier. The carrier is removed to singulate the semiconductor die. A second channel is formed through the plate of the leadframe to physically separate the bodies of the leadframe.