公开(公告)号：US09847238B2

公开(公告)日：2017-12-19

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/02 ,  H01L23/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US09799626B2

公开(公告)日：2017-10-24

申请号：US14852855

申请日：2015-09-14

Applicant: Invensas Corporation

Inventor： Cyprian Uzoh ,  Rajesh Katkar

IPC: H01L21/00 ,  H01L23/12 ,  H01L23/00 ,  H01L21/3213 ,  H01L23/498 ,  H01L21/822 ,  H01L23/31 ,  H01L25/07 ,  H01L25/11 ,  H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L24/97 ,  H01L21/32133 ,  H01L21/486 ,  H01L21/561 ,  H01L21/822 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/072 ,  H01L25/115 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/32013 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/83007 ,  H01L2224/83192 ,  H01L2224/97 ,  H01L2924/07025 ,  H01L2924/15192 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Integrated circuits (ICs 110) are attached to a wafer (120W). A stabilization layer (404) is formed over the wafer to strengthen the structure for further processing. Unlike a conventional mold compound, the stabilization layer is separated from at least some wafer areas around the ICs by one or more gap regions (450) to reduce the thermo-mechanical stress on the wafer and hence the wafer warpage. Alternatively or in addition, the stabilization layer can be a porous material having a low horizontal elastic modulus to reduce the wafer warpage, but having a high flexural modulus to reduce warpage and otherwise strengthen the structure for further processing. Other features and advantages are also provided.

公开(公告)号：US09741696B2

公开(公告)日：2017-08-22

申请号：US15174338

申请日：2016-06-06

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Arkalgud R. Sitaram ,  Cyprian Emeka Uzoh

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/00 ,  H01L23/367 ,  H01L23/42

CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

公开(公告)号：US20170236794A1

公开(公告)日：2017-08-17

申请号：US15584961

申请日：2017-05-02

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/34

CPC classification number: H01L24/09 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/0023 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/34 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/33517 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92133 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

公开(公告)号：US09673124B2

公开(公告)日：2017-06-06

申请号：US15151176

申请日：2016-05-10

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Charles G. Woychik ,  Cyprian Emeka Uzoh

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/13 ,  H01L21/48 ,  H01L21/52 ,  H01L21/54 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/014

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.

公开(公告)号：US20170103957A1

公开(公告)日：2017-04-13

申请号：US14877205

申请日：2015-10-07

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/29 ,  H01L21/56 ,  H01L21/304 ,  H01L23/538 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US20170018529A1

公开(公告)日：2017-01-19

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.

Abstract translation: 微电子组件包括堆叠的半导体芯片，每个半导体芯片具有限定多个平面的相应平面的前表面。 芯片端子可以沿着朝向相应芯片的边缘表​​面的方向从每个芯片的前表面处的触点延伸。 芯片堆叠以一定角度安装到基板，使得芯片的边缘表​​面面向基板的主表面，该主表面限定横向于即不平行于多个平行平面的第二平面。 导电材料将芯片端子与相应的衬底触点电连接。

公开(公告)号：US09496154B2

公开(公告)日：2016-11-15

申请号：US14488187

申请日：2014-09-16

Applicant: Invensas Corporation

Inventor： Eric S. Tosaya ,  Rajesh Katkar ,  Liang Wang ,  Cyprian Emeka Uzoh

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/13 ,  H01L23/3178 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06102 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.

Abstract translation: 微电子部件（110,120）具有凹陷在空腔（410）中并被底部填充带（130）覆盖的接触垫（110C，120C，920C）。 空腔在底部填充带下方具有空隙（410V）。 另一微电子元件的突出的接触垫破坏了底部填充带进入腔并结合到凹陷接触垫。 该空隙有助于破裂底部填充带，从而减少两个接触垫之间的底部填充残余物的量并改善接触电阻。 还提供了一种微电子部件，其具有带有空腔的基板，并且具有延伸到空腔中的贯穿基板。 还提供其他功能。

公开(公告)号：US20160329308A1

公开(公告)日：2016-11-10

申请号：US15217084

申请日：2016-07-22

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Wael Zohni ,  Rizza Lee Saga Cizek ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15312 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

公开(公告)号：US09437536B1

公开(公告)日：2016-09-06

申请号：US14885466

申请日：2015-10-16

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen ,  Cyprian Emeka Uzoh ,  Belgacem Haba

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/498 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1058 ,  H01L2924/1427 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2224/81

Abstract: A method of making an assembly can include forming a circuit structure defining front and rear surfaces, and forming a substrate onto the rear surface. The forming of the circuit structure can include forming a first dielectric layer coupled to the carrier. The first dielectric layer can include front contacts configured for joining with contacts of one or more microelectronic elements, and first traces. The forming of the circuit structure can include forming rear conductive elements at the rear surface coupled with the front contacts through the first traces. The forming of the substrate can include forming a dielectric element directly on the rear surface. The dielectric element can have first conductive elements facing the rear conductive elements and joined thereto. The dielectric element can include second traces coupled with the first conductive elements. The forming of the substrate can include forming terminals at a surface of the substrate.

Abstract translation: 制造组件的方法可以包括形成限定前表面和后表面的电路结构，以及在后表面上形成衬底。 电路结构的形成可以包括形成耦合到载体的第一介电层。 第一电介质层可以包括构造成与一个或多个微电子元件的触点和第一迹线接合的前触点。 电路结构的形成可以包括通过第一迹线在与前触点耦合的后表面处形成后导电元件。 基板的形成可以包括直接在后表面上形成电介质元件。 电介质元件可以具有面向后导电元件并与其连接的第一导电元件。 电介质元件可以包括与第一导电元件耦合的第二迹线。 基板的形成可以包括在基板的表面上形成端子。