公开(公告)号：US20170243761A1

公开(公告)日：2017-08-24

申请号：US15587930

申请日：2017-05-05

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh

IPC: H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/43 ,  H01L24/46 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/023 ,  H01L2224/4502 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A component such as an interposer or microelectronic element can be fabricated with a set of vertically extending interconnects of wire bond structure. Such method may include forming a structure having wire bonds extending in an axial direction within one of more openings in an element and each wire bond spaced at least partially apart from a wall of the opening within which it extends, the element consisting essentially of a material having a coefficient of thermal expansion (“CTE”) of less than 10 parts per million per degree Celsius (“ppm/° C.”). First contacts can then be provided at a first surface of the component and second contacts provided at a second surface of the component facing in a direction opposite from the first surface, the first contacts electrically coupled with the second contacts through the wire bonds.

公开(公告)号：US09691696B2

公开(公告)日：2017-06-27

申请号：US15005220

申请日：2016-01-25

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 620.3) connect the dies to the cavity's bottom wall (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided.

公开(公告)号：US09685420B2

公开(公告)日：2017-06-20

申请号：US15144108

申请日：2016-05-02

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L24/81 ,  H01L21/768 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/10126 ,  H01L2224/1182 ,  H01L2224/13023 ,  H01L2224/13105 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/1379 ,  H01L2224/13809 ,  H01L2224/13811 ,  H01L2224/13847 ,  H01L2224/13855 ,  H01L2224/1601 ,  H01L2224/16014 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16503 ,  H01L2224/16507 ,  H01L2224/81007 ,  H01L2224/81048 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/8181 ,  H01L2224/8182 ,  H01L2224/81862 ,  H01L2224/81895 ,  H01L2224/81903 ,  H01L2224/81905 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01051 ,  H01L2924/01327 ,  H01L2924/364 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/2064

Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.

公开(公告)号：US20170170031A1

公开(公告)日：2017-06-15

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US09666560B1

公开(公告)日：2017-05-30

申请号：US14951892

申请日：2015-11-25

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Guilian Gao ,  Hong Shen ,  Rajesh Katkar ,  Belgacem Haba

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L21/683

CPC classification number: H01L25/0655 ,  H01L21/4846 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/3675 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/116 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a planarized encapsulation. A circuit structure having a thickness less than or equal to 10 microns, formed by depositing two or more dielectric layers and conductive layers on the respective dielectric layers, has electrically conductive features thereon which electrically contact the bumps. The circuit structure can be formed separately on a carrier and then joined with the bumps on the dielectric element, or the circuit structure can be formed by a build up process on the planarized surface of the encapsulation and the planarized surfaces of the bumps.

公开(公告)号：US09666513B2

公开(公告)日：2017-05-30

申请号：US15342744

申请日：2016-11-03

Applicant: Invensas Corporation

Inventor： Ashok S. Prabhu ,  Rajesh Katkar ,  Sean Moran

IPC: H01L23/552 ,  H01L23/495 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49575 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/24 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24175 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: An assembly includes a plurality of stacked encapsulated microelectronic packages, each package including a microelectronic element having a front surface with a plurality of chip contacts at the front surface and edge surfaces extending away from the front surface. An encapsulation region of each package contacts at least one edge surface and extends away therefrom to a remote surface of the package. The package contacts of each package are disposed at a single one of the remote surfaces, the package contacts facing and coupled with corresponding contacts at a surface of a substrate nonparallel with the front surfaces of the microelectronic elements therein.

公开(公告)号：US20160307824A1

公开(公告)日：2016-10-20

申请号：US14686671

申请日：2015-04-14

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/5384 ,  H01L23/5387 ,  H05K1/0203 ,  H05K1/0326 ,  H05K2201/062 ,  H05K2201/10378

Abstract: A substrate structure is presented that can include a porous polyimide material and electrodes formed in the porous polyimide material. In some examples, a method of forming a substrate can include depositing a barrier layer on a substrate; depositing a resist over the barrier layer; patterning and etching the resist; forming electrodes; removing the resist; depositing a porous polyimide aerogel; depositing a dielectric layer over the aerogel material; polishing a top side of the interposer to expose the electrodes; and removing the substrate from the bottom side of the interposer.

Abstract translation: 提出了可以包括多孔聚酰亚胺材料和形成在多孔聚酰亚胺材料中的电极的衬底结构。 在一些实例中，形成衬底的方法可以包括在衬底上沉积阻挡层; 在阻挡层上沉积抗蚀剂; 图案化和蚀刻抗蚀剂; 形成电极; 去除抗蚀剂; 沉积多孔聚酰亚胺气凝胶; 在气凝胶材料上沉积介电层; 抛光插入件的顶侧以露出电极; 以及从所述插入件的底侧移除所述基板。

公开(公告)号：US09455237B2

公开(公告)日：2016-09-27

申请号：US14754293

申请日：2015-06-29

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L21/3213

CPC classification number: H01L24/11 ,  H01L21/3213 ,  H01L21/32139 ,  H01L21/4853 ,  H01L21/76885 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/03462 ,  H01L2224/0348 ,  H01L2224/0362 ,  H01L2224/03823 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05565 ,  H01L2224/05568 ,  H01L2224/05578 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05664 ,  H01L2224/05686 ,  H01L2224/0569 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/11013 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/81815 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In this apparatus, a first metal layer is on the substrate. The first metal layer has an opening. The opening of the first metal layer has a bottom and one or more sides extending from the bottom. A second metal layer is on the first metal layer. The first metal layer and the second metal layer provide a bowl-shaped structure. An inner surface of the bowl-shaped structure is defined responsive to the opening of the first metal layer and the second metal layer thereon. The opening of the bowl-shaped structure is configured to receive and at least partially retain a bonding material during a reflow process.

公开(公告)号：US09412714B2

公开(公告)日：2016-08-09

申请号：US14291874

申请日：2014-05-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Wael Zohni ,  Rizza Lee Saga Cizek ,  Rajesh Katkar

IPC: H01L23/02 ,  H01L23/00 ,  H01L23/34 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/367 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/11318 ,  H01L2224/1132 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/014 ,  H01L2924/15151 ,  H01L2924/15312 ,  H01L2924/15321 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

Abstract translation: 微电子封装可以包括具有第一和第二区域的基板，第一表面和远离第一表面的第二表面; 在所述第一区域内覆盖所述第一表面的至少一个微电子元件; 在第二区域内的第一表面处的导电元件; 支撑结构，其具有第三表面和第四表面，所述第三表面和第四表面远离所述第三表面并且在所述第三区域内的所述第一区域中覆盖所述第一表面，所述第三表面面向所述第一表面， 电连接到第一区域中的第一表面处的导电元件; 以及限定边缘表面并且具有通过第三导电元件中的一个电连接到相应的第二导电元件和远离支撑结构和基座的端部的接合线。

公开(公告)号：US09368479B2

公开(公告)日：2016-06-14

申请号：US14201585

申请日：2014-03-07

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Arkalgud R. Sitaram ,  Cyprian Emeka Uzoh

IPC: H01L23/42 ,  H01L25/065 ,  H01L23/538 ,  H01L21/768 ,  H01L23/48 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

Abstract translation: 装置一般涉及三维堆叠集成电路。 在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。 第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。 所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。 衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。 所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。