公开(公告)号：US20170256496A1

公开(公告)日：2017-09-07

申请号：US15440442

申请日：2017-02-23

Applicant: XINTEC INC.

Inventor： Chia-Sheng LIN ,  Chaung-Lin LAI ,  Kuei-Wei CHEN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/5384 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14683 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02372 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/05008 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0529 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/13211 ,  H01L2224/13216 ,  H01L2224/13244 ,  H01L2224/13247 ,  H01L2224/13255 ,  H01L2924/146 ,  H01L2924/19102 ,  H01L2924/301 ,  H01L2924/00014 ,  H01L2924/013 ,  H01L2924/06 ,  H01L2924/01074

Abstract: A chip package including a substrate is provided. A sensing region or device region of the substrate is electrically connected to a conducting pad. A first insulating layer is disposed on the substrate. A redistribution layer is disposed on the first insulating layer. A first portion and a second portion of the redistribution layer are electrically connected to the conducting pad. A second insulating layer conformally extends on the first insulating layer, and covers side surfaces of the first portion and the second portion. A protection layer is disposed on the second insulating layer. A portion of the second insulating layer is located between the protection layer and the first insulating layer. A method of forming the chip package is also provided.

公开(公告)号：US20170213865A1

公开(公告)日：2017-07-27

申请号：US15410715

申请日：2017-01-19

Applicant: XINTEC INC.

Inventor： Ho-Yin YIU ,  Chi-Chang LIAO ,  Shih-Yi LEE ,  Yen-Kang RAW

IPC: H01L27/146

CPC classification number: H01L27/14621 ,  H01L27/1462 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14685 ,  H01L2224/11

Abstract: This present invention provides a chip scale sensing chip package, comprising: a sensing chip with a first top surface and a first bottom surface opposite to each other, comprising: a sensing device adjacent to the first top surface; and a plurality of conductive pads adjacent to first top surface and the sensing device; a wiring layer formed on the first bottom surface and connected to each of the conductive pads; a dam having a supporter with a first opening and a spacer with a second opening formed on the first top surface, wherein the supporter is within the second opening and adjacent to the spacer, and the spacer is higher than the supporter by a predetermined distance d; a lens formed on the first top surface exposed by the first opening and above the sensing device; and an optical filter deposed on the supporter and above the lens.

公开(公告)号：US20170207182A1

公开(公告)日：2017-07-20

申请号：US15409289

申请日：2017-01-18

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Tsang-Yu LIU ,  Chia-Sheng LIN ,  Chaung-Lin LAI

IPC: H01L23/00 ,  H01L23/18 ,  H01L21/78 ,  H01L21/54 ,  H01L21/52 ,  H01L23/055 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/54 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/055 ,  H01L23/18 ,  H01L23/3114 ,  H01L23/522 ,  H01L24/16 ,  H01L25/065 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/16237

Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing or device region which is adjacent to the first surface. A recess is in the substrate. The recess extends from the second surface towards the first surface, and vertically overlaps the sensing or device region. A redistribution layer is electrically connected to the sensing or device region, and extends from the second surface into the recess. A method of forming the chip package is also provided.

公开(公告)号：US09640683B2

公开(公告)日：2017-05-02

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0203 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09570398B2

公开(公告)日：2017-02-14

申请号：US13895219

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Ting Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  B81B7/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/60

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US20170012081A1

公开(公告)日：2017-01-12

申请号：US15181288

申请日：2016-06-13

Applicant: XINTEC INC.

Inventor： Chia-Lun SHEN ,  Yi-Ming CHANG ,  Hsiao-Lan YEH ,  Yen-Shih HO

IPC: H01L27/146 ,  H01L21/78 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L27/14687 ,  H01L21/78 ,  H01L24/03 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14636 ,  H01L2224/0331 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06132 ,  H01L2224/06135 ,  H01L2224/11005 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14132 ,  H01L2224/14179 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17135 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/818 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06568 ,  H01L2924/3511 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A manufacturing method of a chip package includes the following steps. A patterned solder paste layer is printed on a patterned conductive layer of a wafer. Plural solder balls are disposed on the solder paste layer that is on a first portion of the conductive layer. A reflow process is performed on the solder balls and the solder paste layer. A flux layer converted from a surface of the solder paste layer is cleaned.

Abstract translation: 芯片封装的制造方法包括以下步骤。 将图案化的焊膏层印刷在晶片的图案化导电层上。 多个焊球设置在导电层的第一部分上的焊膏层上。 在焊球和焊膏层上进行回流处理。 从焊膏层的表面转换的焊剂层被清洁。

公开(公告)号：US20160315048A1

公开(公告)日：2016-10-27

申请号：US15138167

申请日：2016-04-25

Applicant: XINTEC INC.

Inventor： Yen-Shih HO ,  Shu-Ming CHANG ,  Hsing-Lung SHEN ,  Yu-Hao SU ,  Kuan-Jung WU ,  Yi CHENG

IPC: H01L23/522 ,  H01L23/48 ,  H01L21/768 ,  H01L21/288 ,  C25D17/08 ,  H01L49/02 ,  H01L21/673 ,  H01L21/677 ,  C25D17/00 ,  C25D7/12 ,  H01L27/144 ,  H01L21/3205

CPC classification number: H01L23/49838 ,  C25D17/001 ,  C25D17/005 ,  C25D17/06 ,  H01L21/2885 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/68721 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L28/10 ,  H01L2224/11

Abstract: A semiconductor electroplating system includes a conducting ring and at least one conductive device. The conducting ring is used for carrying a wafer. The conducting ring has at least two connecting points. The wafer has a first surface and an opposite second surface. An isolation layer is located on the second surface. Two ends of the conductive device are respectively connected to the two connecting points of the conducting ring. When the conducting ring is immersed in the plating solution and is energized, a redistribution layer that is to be patterned is formed on the isolation layer. The conductive device is used for transmitting a partial current that passes through one of the connecting points to the other connecting point.

Abstract translation: 半导体电镀系统包括导电环和至少一个导电装置。 导电环用于承载晶片。 导电环具有至少两个连接点。 晶片具有第一表面和相对的第二表面。 隔离层位于第二表面上。 导电装置的两端分别连接到导电环的两个连接点。 当导电环浸入电镀溶液中并通电时，在隔离层上形成待图案化的再分配层。 导电装置用于将通过其中一个连接点的部分电流传送到另一个连接点。

公开(公告)号：US20160240520A1

公开(公告)日：2016-08-18

申请号：US15007124

申请日：2016-01-26

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Shu-Ming Chang ,  Hsing-Lung Shen

IPC: H01L25/16 ,  H01L21/304 ,  H01L21/78 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/486 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02375 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/05032 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A chip package includes a chip, a dielectric bonding layer, a carrier, and a redistribution layer. The chip has a substrate, a conductive pad, and a protection layer. The dielectric bonding layer is located on the protection layer and between the carrier and the protection layer. The carrier, the dielectric bonding layer, and the protection layer have a communicated through hole configured to expose the conductive pad. The redistribution layer includes a connection portion and a passive component portion. The connection portion is located on the conductive pad, the sidewall of the through hole, and a surface of the carrier facing away from the dielectric bonding layer. The passive component portion is located on the surface of the carrier, and an end of the passive component portion is connected to the connection portion that is on the surface of the carrier.

Abstract translation: 芯片封装包括芯片，电介质结合层，载体和再分配层。 芯片具有基板，导电焊盘和保护层。 电介质接合层位于保护层上，载体和保护层之间。 载体，介电接合层和保护层具有被配置为暴露导电垫的连通通孔。 再分配层包括连接部分和无源部件部分。 连接部分位于导电垫上，通孔的侧壁和载体的表面背离电介质结合层。 无源部件位于载体的表面上，无源部件的一端与载体表面上的连接部分连接。

公开(公告)号：US20160229687A1

公开(公告)日：2016-08-11

申请号：US15008371

申请日：2016-01-27

Applicant: XINTEC INC.

Inventor： Ying-Nan WEN ,  Ho-Yin YIU ,  Chien-Hung LIU

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00293 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract translation: 芯片封装包括芯片，第一通孔，激光停止结构，第一隔离层，第二通孔和导电层。 第一通孔从芯片的第二表面延伸到第一表面以暴露导电焊盘，并且激光停止结构设置在由第一通孔暴露的导电焊盘上，激光停止结构的上表面 在第二个表面之上。 第一隔离层覆盖第二表面和激光停止结构，第一隔离层具有与第二表面相对的第三表面。 第二通孔从第三表面延伸到第二表面以暴露激光停止结构，并且导电层在第三表面上并延伸到第二通孔中以接触激光停止结构。

公开(公告)号：US09403672B2

公开(公告)日：2016-08-02

申请号：US14819174

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Chien-Min Lin

IPC: B81B7/00 ,  H01L21/48 ,  B81C1/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2207/096 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2203/0118 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.

Abstract translation: 一种方法包括在插入器的下表面上形成凸块。 形成第一绝缘层以覆盖下表面和凸起。 形成从插入件的下表面延伸到上表面的沟槽。 形成聚合物支持粘合剂层以围绕凸起并且在插入器和半导体芯片之间耦合。 半导体芯片具有至少一个感测部件和电连接到感测部件的导电焊盘，并且凸块连接到导电焊盘。 通孔形成为从上部向下表面延伸。 形成第二绝缘层以覆盖上表面和通孔。 在第二绝缘层和通孔中形成再分布层。 形成包装层以覆盖再分布层并具有第二开口。