公开(公告)号：US20180027700A1

公开(公告)日：2018-01-25

申请号：US15396647

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Aaron Gorius ,  Michael T. Crocker ,  Myles Wilde

IPC: H05K7/20 ,  G02B6/38 ,  G02B6/44 ,  H05K7/14

CPC classification number: H04Q11/0005 ,  B25J15/0014 ,  B65G1/0492 ,  G02B6/3882 ,  G02B6/3893 ,  G02B6/3897 ,  G02B6/4292 ,  G02B6/4452 ,  G05D23/1921 ,  G05D23/2039 ,  G06F1/183 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0664 ,  G06F3/0665 ,  G06F3/067 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0683 ,  G06F3/0688 ,  G06F3/0689 ,  G06F8/65 ,  G06F9/4401 ,  G06F9/5016 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/5072 ,  G06F9/5077 ,  G06F11/141 ,  G06F11/3414 ,  G06F12/0862 ,  G06F12/0893 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1408 ,  G06F13/161 ,  G06F13/1668 ,  G06F13/1694 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/409 ,  G06F13/42 ,  G06F13/4282 ,  G06F15/8061 ,  G06F17/30949 ,  G06F2209/5019 ,  G06F2209/5022 ,  G06F2212/1008 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/202 ,  G06F2212/401 ,  G06F2212/402 ,  G06F2212/7207 ,  G06Q10/06 ,  G06Q10/06314 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  G07C5/008 ,  G08C17/02 ,  G08C2200/00 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1072 ,  G11C11/56 ,  G11C14/0009 ,  H03M7/30 ,  H03M7/3084 ,  H03M7/3086 ,  H03M7/40 ,  H03M7/4031 ,  H03M7/4056 ,  H03M7/4081 ,  H03M7/6005 ,  H03M7/6023 ,  H04B10/25 ,  H04B10/2504 ,  H04L9/0643 ,  H04L9/14 ,  H04L9/3247 ,  H04L9/3263 ,  H04L12/2809 ,  H04L29/12009 ,  H04L41/024 ,  H04L41/046 ,  H04L41/0813 ,  H04L41/082 ,  H04L41/0896 ,  H04L41/12 ,  H04L41/145 ,  H04L41/147 ,  H04L41/5019 ,  H04L43/065 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L43/16 ,  H04L45/02 ,  H04L45/52 ,  H04L47/24 ,  H04L47/765 ,  H04L47/782 ,  H04L47/805 ,  H04L47/82 ,  H04L47/823 ,  H04L49/15 ,  H04L49/25 ,  H04L49/357 ,  H04L49/45 ,  H04L49/555 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1004 ,  H04L67/1008 ,  H04L67/1012 ,  H04L67/1014 ,  H04L67/1029 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H04L67/16 ,  H04L67/306 ,  H04L67/34 ,  H04L69/04 ,  H04L69/329 ,  H04Q1/04 ,  H04Q11/00 ,  H04Q11/0003 ,  H04Q11/0062 ,  H04Q11/0071 ,  H04Q2011/0037 ,  H04Q2011/0041 ,  H04Q2011/0052 ,  H04Q2011/0073 ,  H04Q2011/0079 ,  H04Q2011/0086 ,  H04Q2213/13523 ,  H04Q2213/13527 ,  H04W4/023 ,  H04W4/80 ,  H05K1/0203 ,  H05K1/181 ,  H05K5/0204 ,  H05K7/1418 ,  H05K7/1421 ,  H05K7/1422 ,  H05K7/1447 ,  H05K7/1461 ,  H05K7/1485 ,  H05K7/1487 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/2039 ,  H05K7/20709 ,  H05K7/20727 ,  H05K7/20736 ,  H05K7/20745 ,  H05K7/20836 ,  H05K13/0486 ,  H05K2201/066 ,  H05K2201/10121 ,  H05K2201/10159 ,  H05K2201/10189 ,  Y10S901/01

Abstract: A rack for supporting a sleds includes a pair of elongated support posts and pairs of elongated support arms that extend from the elongated support posts. Each pair of the elongated support arms defines a sled slot to receive a corresponding sled. To do so, each elongated support arm includes a circuit board guide to receive a chassis-less circuit board substrate of the corresponding sled. The rack may include a cross-member arm associated with each sled slot and an optical connector mounted to each cross-member arm. Additional elongated support posts may be used to provide additional sled slots.

公开(公告)号：US20250062278A1

公开(公告)日：2025-02-20

申请号：US18452152

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

公开(公告)号：US11595277B2

公开(公告)日：2023-02-28

申请号：US17404749

申请日：2021-08-17

Applicant: Intel Corporation

Inventor： Matthew Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Michael Crocker

IPC: H04L43/08 ,  G06F16/901 ,  H04B10/25 ,  G02B6/38 ,  G02B6/42 ,  G02B6/44 ,  G06F1/18 ,  G06F1/20 ,  G06F3/06 ,  G06F8/65 ,  G06F9/30 ,  G06F9/4401 ,  G06F9/54 ,  G06F12/109 ,  G06F12/14 ,  G06F13/16 ,  G06F13/40 ,  G08C17/02 ,  G11C5/02 ,  G11C7/10 ,  G11C11/56 ,  G11C14/00 ,  H03M7/30 ,  H03M7/40 ,  H04L41/14 ,  H04L43/0817 ,  H04L43/0876 ,  H04L43/0894 ,  H04L49/00 ,  H04L49/25 ,  H04L49/356 ,  H04L49/45 ,  H04L67/02 ,  H04L67/306 ,  H04L69/04 ,  H04L69/329 ,  H04Q11/00 ,  H05K7/14 ,  G06F15/16 ,  G06F9/38 ,  G06F9/50 ,  H04L41/12 ,  H04L41/5019 ,  H04L43/16 ,  H04L47/24 ,  H04L47/38 ,  H04L67/1004 ,  H04L67/1034 ,  H04L67/1097 ,  H04L67/12 ,  H05K5/02 ,  H04W4/80 ,  G06Q10/087 ,  G06Q10/20 ,  G06Q50/04 ,  H04L43/065 ,  H04J14/00 ,  H04L61/00 ,  H04L67/51 ,  H04L41/147 ,  H04L67/1008 ,  H04L41/0813 ,  H04L67/1029 ,  H04L41/0896 ,  H04L47/70 ,  H04L47/78 ,  H04L41/082 ,  H04L67/00 ,  H04L67/1012 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L49/55 ,  H04L67/10 ,  H04W4/02 ,  H04L45/02 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L47/80 ,  H05K1/02 ,  H04L45/52 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L47/765 ,  H04L67/1014 ,  G06F12/10 ,  G06Q10/06 ,  G06Q10/0631 ,  G07C5/00 ,  H04L12/28 ,  H04L41/02 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L41/046 ,  H04L49/15

Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

公开(公告)号：US20220407317A1

公开(公告)日：2022-12-22

申请号：US17354939

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Aaron Gorius ,  Tod Schiff ,  Andrew Keates

IPC: H02J7/00

Abstract: A microcontroller, processor, and/or software (SW) monitors a battery degradation indicator such as battery State-Of-Health (SOH), impedance or other attributes, and calculates battery degradation rate and regulates burst power, battery charging speed and/or battery charging limit to meet users' expectation of battery service life. The microcontroller, processor, and/or SW increases the burst power, battery charging speed and/or battery charging limit when 1/SOH or impedance change rate (or related parameter) is smaller than expected and there is more longevity budget than expected. In another example, the microcontroller, processor, and/or SW decreases the burst power, battery charging speed and/or battery charging limit when 1/SOH or impedance change rate (or related parameter) is greater than expected and there is less longevity budget than expected.

公开(公告)号：US11237840B2

公开(公告)日：2022-02-01

申请号：US16091201

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Matthew J. Adiletta ,  Myles Wilde ,  Michael F. Fallon ,  Amit Kumar ,  Chengda Yang ,  Aaron Gorius ,  William R. Wheeler

IPC: G06F9/00 ,  G06F9/4401 ,  G06F1/16 ,  G06F13/40 ,  G06K19/04

Abstract: All in one mobile computing devices and methods performed by the devices. The all in one mobile computing device includes a processor, memory, and software instructions configured to be executed on the processor to enable the mobile computing device to perform various operations. The all in one device may include various wired and wireless interfaces that enable it to communicate with a wide-range of devices, including smartphones, tablets, laptops, personal computers, smart TVs, and others. The all in one device is capable of being remotely accessed when linked in communication with a second device, and is enabled to aggregate data from various user devices and cloud-based services to create unified data resources. Data that is accessed by the device may be synched with a cloud-based storage service to enable a user to access data from across a range of devices via the all in one device. The all in one device has a form factor that is approximately the size of a credit card, yet is capable of running a full-fledged desktop operating system.

公开(公告)号：US10985587B2

公开(公告)日：2021-04-20

申请号：US16057588

申请日：2018-08-07

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Simon N. Peffers ,  Steven Lloyd ,  Michael T. Crocker ,  Aaron Gorius

IPC: H02J7/00

Abstract: In some examples, a control unit is configured to adjust charge termination voltage of a rechargeable energy storage device. The control unit is adapted to charge the rechargeable energy storage device to a charge termination voltage where the rechargeable energy storage device has capacity to support peak load but comes close to a system shutdown voltage after supporting peak load. The control unit is also adapted to increase the charge termination voltage if a voltage of the rechargeable energy storage device is near a system shutdown voltage after supporting peak load.

公开(公告)号：US10910746B2

公开(公告)日：2021-02-02

申请号：US16208543

申请日：2018-12-03

Applicant: Intel Corporation

Inventor： Russell Aoki ,  Aaron Gorius ,  Michael T. Crocker ,  Matthew J. Adiletta

IPC: H01R12/00 ,  H01R12/72 ,  H05K1/14 ,  G06F1/18 ,  H05K7/18

Abstract: Sleds for operation in racks of data centers are disclosed herein. A sled includes a circuit board substrate, one or more physical resources, and one or more memory devices. The circuit board substrate has a top side and a bottom side arranged opposite the top side. The one or more physical resources are coupled to the top side of the circuit board substrate. The one or more memory devices are coupled to the bottom side of the circuit board substrate. Additionally, the sled includes a connector to electrically couple the one or more physical resources to the one or more memory devices.

公开(公告)号：US20190342642A1

公开(公告)日：2019-11-07

申请号：US16513345

申请日：2019-07-16

Applicant: Intel Corporation

Inventor： Matthew Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Michael Crocker

IPC: H04Q11/00 ,  G06F16/901 ,  H04L12/811 ,  H03M7/30 ,  H03M7/40 ,  H04L12/24 ,  H04L12/933 ,  H04L12/931 ,  G06Q10/06 ,  G07C5/00 ,  G06F13/40 ,  G06F13/16 ,  G06F9/50 ,  G06F15/80 ,  G06F11/34 ,  G06F11/14 ,  G11C5/06 ,  H05K13/04 ,  G06F13/42 ,  H04Q1/04 ,  H04L12/781 ,  G06F3/06 ,  G06F9/4401 ,  G06F12/14 ,  G06F8/65 ,  G11C11/56 ,  G11C5/02 ,  G11C14/00 ,  H04L12/911 ,  G08C17/02 ,  H04L12/947 ,  H04L29/08 ,  H04L9/32 ,  H04L9/14 ,  H04L9/06 ,  H04L12/28 ,  H04L29/12 ,  G06F12/10 ,  H04L12/919 ,  G06F12/0862 ,  H05K7/14 ,  G06F12/0893 ,  H05K1/02 ,  H04L12/927 ,  H05K7/20 ,  G05D23/20 ,  G05D23/19 ,  H05K1/18 ,  H04L12/751 ,  H04L12/939 ,  H04W4/02 ,  B25J15/00 ,  B65G1/04 ,  H04B10/25 ,  H04L12/26 ,  H04L29/06 ,  G06F12/109 ,  H04L12/851 ,  H05K5/02 ,  G06F1/18 ,  G11C7/10 ,  G06F9/54 ,  G06F9/38 ,  G06F9/30 ,  G02B6/42 ,  G02B6/38 ,  G02B6/44

Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

公开(公告)号：US10397670B2

公开(公告)日：2019-08-27

申请号：US15425916

申请日：2017-02-06

Applicant: INTEL CORPORATION

Inventor： Aaron Gorius ,  Myles Wilde ,  Matthew J. Adiletta

IPC: H03M7/40 ,  H04L12/24 ,  H04L12/931 ,  H04L12/851 ,  H04L12/781 ,  G06F13/40 ,  H04Q11/00 ,  H04B10/25 ,  H03M7/30 ,  G06F16/901 ,  G06F3/06 ,  G11C7/10 ,  H05K7/14 ,  G06F1/18 ,  H05K5/02 ,  G08C17/02 ,  H04L29/08 ,  H04L12/26 ,  G06F9/50 ,  H04L12/911 ,  G06F12/109 ,  H04L29/06 ,  G11C14/00 ,  G11C5/02 ,  G11C11/56 ,  G02B6/44 ,  G06F8/65 ,  G06F12/14 ,  G06F13/16 ,  G06F9/4401 ,  G02B6/38 ,  G02B6/42 ,  B25J15/00 ,  B65G1/04 ,  H05K7/20 ,  H04L12/939 ,  H04W4/02 ,  H04L12/751 ,  G06F13/42 ,  H05K1/18 ,  G05D23/19 ,  G05D23/20 ,  H04L12/927 ,  H05K1/02 ,  H04Q1/04 ,  G06F12/0893 ,  H05K13/04 ,  G11C5/06 ,  G06F11/14 ,  G06F11/34 ,  G06F12/0862 ,  G06F15/80 ,  H04L12/919 ,  G06F12/10 ,  G06Q10/06 ,  G07C5/00 ,  H04L12/28 ,  H04L29/12 ,  H04L9/06 ,  H04L9/14 ,  H04L9/32 ,  H04L12/933 ,  H04L12/947 ,  H04L12/811 ,  H04W4/80 ,  G06Q10/08 ,  G06Q10/00 ,  G06Q50/04

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to receive a packet via an optical fabric, the packet comprising a switch mode indicator, determine a switch mode for the packet based on the switch mode indicator, and process the packet in accordance with a first protocol or a second protocol based on the switch mode.

公开(公告)号：US20190141845A1

公开(公告)日：2019-05-09

申请号：US16220631

申请日：2018-12-14

Applicant: Intel Corporation

Inventor： Mani Prakash ,  Thomas T. Holden ,  Aaron Gorius ,  Michael T. Crocker ,  Matthew J. Adiletta ,  Russell Aoki

IPC: H05K5/00 ,  H05K5/02 ,  H05K7/02

Abstract: A configurable processor module includes a central processing unit (CPU) package mounted to a CPU substrate, which may be mounted to a circuit board substrate. The CPU substrate may include physical resources usable by the CPU package, which may not be included or duplicated on the circuit board substrate. As such, features of the CPU package that are unavailable on the circuit board substrate may be available on the CPU substrate. Additionally, the CPU substrate and physical resources may be selected and designed so as to provide varying levels of functionality across different compute devices that use the same type of CPU package.