公开(公告)号：US20180061849A1

公开(公告)日：2018-03-01

申请号：US15602448

申请日：2017-05-23

Applicant: Renesas Electronics Corporation

Inventor： Tadashi YAMAGUCHI

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L29/45 ,  H01L21/768 ,  H01L29/06

CPC classification number: H01L27/11568 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/42344 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/785

Abstract: Performance and reliability of a semiconductor device are improved. An insulating film is formed such that a control gate electrode, a memory gate electrode, and a gate electrode are embedded, and then tops of the control gate electrode, the memory gate electrode, and the gate electrode are exposed by first polishing. Subsequently, a trench is formed by removing the gate electrode and filled with a metal film, and second polishing is performed to form a gate electrode including the metal film. The insulating film is an O3-TEOS film having a high gap filling characteristic, and thus reduces formation of a seam in the insulating film. Furthermore, the O3-TEOS film is subjected to heat treatment in an oxidizing atmosphere before the first polishing, thereby dishing of the insulating film is reduced during the second polishing.

公开(公告)号：US20170291915A1

公开(公告)日：2017-10-12

申请号：US15512968

申请日：2015-09-23

Applicant: Claudia FAFARD ,  Venkateswara R. PALLEM ,  Jean-Marc GIRARD ,  American Air Liquide, Inc.

Inventor： Claudia FAFARD ,  Venkateswara R. PALLEM ,  Jean-Marc GIRARD

IPC: C07F7/10 ,  H01L21/02 ,  C23C16/455 ,  C07F7/08 ,  C23C16/24

CPC classification number: C07F7/10 ,  C07F7/02 ,  C07F7/08 ,  C23C16/24 ,  C23C16/30 ,  C23C16/325 ,  C23C16/345 ,  C23C16/36 ,  C23C16/401 ,  C23C16/402 ,  C23C16/45553 ,  H01L21/02123 ,  H01L21/0228 ,  H01L21/02532

Abstract: Disclosed are Si-containing film forming compositions comprising carbosilane substituted amine precursors. The carbosilane substituted amine precursors have the formula (R1)aN(—SiHR2—CH2—SiH2R3)3-a, wherein a=0 or 1; R1 is H, a C1 to C6 alkyl group, or a halogen; R2 and R3 is each independently H; a halogen; an alkoxy group having the formula OR′, wherein R′ is an alkyl group (C1 to C6); or an alkylamino group having the formula NR″2, wherein each R″ is independently H, a C1-C6 alkyl group, a C1-C6 alkenyl group, or a C3-C10 aryl or heterocycle group. Also disclosed are methods of synthesizing the carbosilane substituted amine precursors and their use for deposition processes.

公开(公告)号：US20170271196A1

公开(公告)日：2017-09-21

申请号：US15461847

申请日：2017-03-17

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Ludovic Godet ,  Rui Cheng ,  Erica Chen ,  Ziqing Duan ,  Abhijit Basu Mallick ,  Srinivas Gandikota

IPC: H01L21/762 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02123 ,  H01L21/76283 ,  H01L21/76286 ,  H01L21/76837 ,  H01L23/3178 ,  H01L29/0649

Abstract: Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

公开(公告)号：US20170207083A1

公开(公告)日：2017-07-20

申请号：US15349359

申请日：2016-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunhye HWANG ,  Myong Woon KIM ,  Younjoung CHO ,  Sang lck LEE ,  Sang Yong JEON ,  In Kyung JUNG ,  Wonwoong CHUNG ,  Jungsik CHOI

IPC: H01L21/02 ,  H01L21/768 ,  C01B33/12

CPC classification number: H01L21/02208 ,  C01B33/126 ,  C23C16/00 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02214 ,  H01L21/02274 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5329 ,  H01L2221/1047

Abstract: A method of forming a dielectric layer includes forming a preliminary dielectric layer on a substrate using a silicon precursor and performing an energy treatment on the preliminary dielectric layer to form a dielectric layer. In the dielectric layer, a ratio of Si—CH3 bonding unit to Si—O bonding unit ranges from 0.5 to 5.

公开(公告)号：US09691519B2

公开(公告)日：2017-06-27

申请号：US14085377

申请日：2013-11-20

Applicant: NAPRA CO., LTD.

Inventor： Shigenobu Sekine ,  Yurina Sekine

IPC: B05D3/02 ,  H01B3/18 ,  H01B3/46 ,  H01B13/06 ,  H01B3/00 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01B3/18 ,  H01B3/006 ,  H01B3/46 ,  H01B13/06 ,  H01L21/02123 ,  H01L21/02282 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An insulating paste includes insulating particles 311, Si particles 312 and an organic Si compound 320. The organic Si compound 320 reacts with the Si particles 312 to form a Si—O bond filling up the space around the insulating particles 311.

公开(公告)号：US20170148676A1

公开(公告)日：2017-05-25

申请号：US15425558

申请日：2017-02-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joung-Wei Liou ,  Hui-Chun Yang ,  Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76879 ,  H01L21/02123 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02321 ,  H01L21/76801 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/31 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The porogen comprises an organic ring structure with fewer than fifteen carbons and a large percentage of single bonds. Additionally, the porogen may have a viscosity greater than 1.3 and a Reynolds numbers less than 0.5.

公开(公告)号：US20170148628A1

公开(公告)日：2017-05-25

申请号：US15426889

申请日：2017-02-07

Applicant: Novellus Systems, Inc.

Inventor： Shankar Swaminathan ,  Jon Henri ,  Dennis Hausmann ,  Pramod Subramonium ,  Mandyam Sriram ,  Vishwanathan Rangarajan ,  Kirthi Kattige ,  Bart van Schravendijk ,  Andrew J. McKerrow

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/52 ,  C23C16/44 ,  C23C16/455 ,  C23C16/04 ,  C23C16/40

CPC classification number: H01L21/02123 ,  C23C16/045 ,  C23C16/345 ,  C23C16/401 ,  C23C16/402 ,  C23C16/4408 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/4554 ,  C23C16/45544 ,  C23C16/52 ,  C23C16/56 ,  H01J37/32412 ,  H01J2237/3321 ,  H01J2237/3365 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/67017 ,  H01L21/76831 ,  H01L21/76898

Abstract: Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by intermittent delivery of dopant species to the film between the cycles of adsorption and reaction.

公开(公告)号：US09607825B2

公开(公告)日：2017-03-28

申请号：US14247559

申请日：2014-04-08

Applicant: International Business Machines Corporation

Inventor： Donald Francis Canaperi ,  Alfred Grill ,  Sanjay C. Mehta ,  Son Van Nguyen ,  Deepika Priyadarshini ,  Hosadurga Shobha ,  Matthew T. Shoudy

IPC: H01L21/20 ,  H01L21/02 ,  H01L23/532 ,  H01L29/51 ,  C23C16/34 ,  C23C16/40 ,  C23C16/455 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L23/485

CPC classification number: H01L21/02274 ,  C23C16/345 ,  C23C16/401 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/50 ,  H01L21/02123 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02219 ,  H01L21/02299 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/42364 ,  H01L29/4983 ,  H01L29/511 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide hydrogen-free dielectric films and methods of fabrication. A hydrogen-free precursor, such as tetraisocyanatosilane, and hydrogen-free reactants, such as nitrogen, oxygen (O2/O3) and nitrous oxide are used with chemical vapor deposition processes (PECVD, thermal CVD, SACVD, HDP CVD, and PE and Thermal ALD) to create hydrogen-free dielectric films. In some embodiments, there are multilayer dielectric films with sublayers of various materials such as silicon oxide, silicon nitride, and silicon oxynitride. In embodiments, the hydrogen-free reactants may include Tetra Isocyanato Silane, along with a hydrogen-free gas including, but not limited to, N2, O2, O3, N2O, CO2, CO and a combination thereof of these H-Free gases. Plasma may be used to enhance the reaction between the TICS and the other H-free gasses. The plasma may be controlled during film deposition to achieve variable density within each sublayer of the films.

公开(公告)号：US20170076956A1

公开(公告)日：2017-03-16

申请号：US15308212

申请日：2015-05-20

Applicant: TOKYO ELECTRON LIMITED

Inventor： Yusuke HIRAYAMA ,  Masaaki MIYAGAWA

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/31116 ,  C23C16/4404 ,  C23C16/4405 ,  H01J37/32009 ,  H01J37/32165 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32477 ,  H01J37/3266 ,  H01J2237/334 ,  H01L21/02115 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/205 ,  H01L21/3065 ,  H01L21/67069 ,  H05H1/46

Abstract: This plasma processing method includes a film formation step, a plasma processing step and a removal step. In the film formation step, a silicon oxide film is formed on the surface of a member within a chamber by means of plasma of an oxygen-containing gas and a silicon-containing gas at a flow rate ratio of the oxygen-containing gas to the silicon-containing gas of 0.2-1.4. In the plasma processing step, after the formation of the silicon oxide film on the surface of the member, an object to be processed that has been carried into the chamber is subjected to plasma processing with use of plasma of a processing gas. In the removal step, after carrying the plasma-processed object out of the chamber, the silicon oxide film is removed from the surface of the member by means of plasma of a fluorine-containing gas.

Abstract translation: 该等离子体处理方法包括成膜步骤，等离子体处理步骤和去除步骤。 在成膜步骤中，通过含氧气体和含硅气体的等离子体以含氧气体的流量比为基准，在室内部件的表面上形成氧化硅膜 含硅气体为0.2-1.4。 在等离子体处理步骤中，在构件表面上形成氧化硅膜之后，使用处理气体的等离子体对被搬运到室内的待处理物进行等离子体处理。 在去除步骤中，在将等离子体处理物体搬出室外之后，通过含氟气体的等离子体从构件的表面除去氧化硅膜。

公开(公告)号：US20170062429A1

公开(公告)日：2017-03-02

申请号：US15172201

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu SUNG ,  Neeraj TRIPATHI

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/167

CPC classification number: H01L27/0924 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/66818

Abstract: A method of forming a fin liner and the resulting device are provided. Embodiments include forming silicon (Si) fins over negative channel field-effect transistor (nFET) and positive channel field-effect transistor (pFET) regions of a substrate, each of the Si fins having a silicon nitride (SiN) cap; forming a SiN liner over the Si fins and SiN caps; forming a block mask over the pFET region; removing the SiN liner in the nFET region; removing the block mask in the pFET region; forming a diffusion barrier liner over the Si fins; forming a dielectric layer over and between the Si fins; planarizing the dielectric layer down to the SiN caps in the nFET region; and recessing the dielectric layer to expose an upper portion of the Si fins.

Abstract translation: 提供了形成翅片衬垫的方法和所得到的装置。 实施例包括在衬底的负沟道场效应晶体管（nFET）和正沟道场效应晶体管（pFET）区域上形成硅（Si）鳍，每个Si散热片具有氮化硅（SiN）帽; 在Si翅片和SiN帽上形成SiN衬垫; 在所述pFET区域上形成块掩模; 去除nFET区域中的SiN衬垫; 去除pFET区域中的块掩模; 在Si散热片上形成扩散阻挡衬垫; 在Si散热片之上和之间形成介电层; 将电介质层平坦化到nFET区域中的SiN帽; 并使介电层凹陷以暴露Si散热片的上部。