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公开(公告)号：US11839018B2
公开(公告)日：2023-12-05
申请号：US17427110
申请日：2020-12-17
Inventor： Wenxiao Niu , Xinpeng Wang , Hengzhen Liang , Xiaolong Zhu , Lianbin Liu
CPC classification number: H05K1/0218 , G06F3/04164 , H05K1/0281 , H05K1/189 , G06F3/0412 , G06F3/0446 , H05K2201/0715 , H05K2201/09027 , H05K2201/09036 , H05K2201/09227 , H05K2201/09245 , H05K2201/09509 , H05K2201/10128 , H05K2201/10189 , H05K2201/2009 , H10K59/131 , H10K59/40
Abstract: A flexible printed circuit board and a display touch apparatus are provided. The flexible printed circuit board includes a binding terminal region, a first circuit region and a second circuit region; the binding terminal region includes multiple terminals, the first circuit region includes a driver circuit, multiple first signal lines, multiple second signal lines, and multiple third signal lines, and the second circuit region includes an external connector; first ends of the multiple first signal lines, the multiple second signal lines and the multiple third signal lines are respectively connected to the terminals of the binding terminal region; second ends of the multiple first signal lines and the multiple second signal lines are respectively connected to the driver circuit; and second ends of the multiple third signal lines are connected to the connector.
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公开(公告)号：US11764540B2
公开(公告)日：2023-09-19
申请号：US17620729
申请日：2020-06-30
Applicant: LANDA LABS (2012) LTD.
Inventor： Ronny Costi , Gilad Reut Gelbart
IPC: H01S5/02315 , H01S5/0237 , H01S5/02345 , H01S5/02 , H01S5/024 , H05K1/02 , H05K1/11 , H05K3/42
CPC classification number: H01S5/02315 , H01S5/0216 , H01S5/0237 , H01S5/02345 , H01S5/02469 , H01S5/02476 , H05K1/0206 , H05K1/0209 , H05K1/113 , H05K1/118 , H05K3/422 , H05K2201/09445 , H05K2201/09509 , H05K2203/073
Abstract: A method is disclosed for mounting and cooling a circuit component having a plurality of contacts. The method comprises mounting the circuit component on a rigid substrate of a thermally conductive material having and electrically insulating regions with a circuit board arranged between the circuit component and the substrate. The circuit board, which carries conductive traces that terminate in contact pads, is secured to the substrate with at least some of the contact pads on the circuit board disposed on the side of the board facing the substrate, some of which being bonded to the substrate. To establish both an electrical and a thermal connection between the contacts of the circuit component and the contact pads bonded to the substrate, blind holes are formed in the base of the circuit board, each hole terminating at a respective one of the contact pads bonded to the substrate.
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公开(公告)号：US11678441B2
公开(公告)日：2023-06-13
申请号：US16950910
申请日：2020-11-18
Applicant: Unimicron Technology Corp.
Inventor： Wei-Ti Lin , Chun-Hsien Chien , Chien-Chou Chen , Fu-Yang Chen , Ra-Min Tain
CPC classification number: H05K3/4644 , H05K1/111 , H05K1/115 , H05K1/181 , H05K3/007 , H05K3/0097 , H05K3/28 , H05K3/303 , H05K3/4007 , H05K3/421 , H05K3/429 , H05K2201/09136 , H05K2201/09509 , H05K2201/09827 , H05K2201/10234 , H05K2201/10522
Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
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公开(公告)号：US20230164928A1
公开(公告)日：2023-05-25
申请号：US17945106
申请日：2022-09-15
Applicant: Unimicron Technology Corp.
Inventor： Cheng-Ta Ko , Pu-Ju Lin , Shih-Chieh Chen , Chi-Hai Kuo , Jeng-Ting Li
CPC classification number: H05K3/4691 , H05K1/0393 , H05K1/118 , H05K3/06 , H05K2201/0154 , H05K2201/09509
Abstract: A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.
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公开(公告)号：US20230156909A1
公开(公告)日：2023-05-18
申请号：US17873153
申请日：2022-07-26
Applicant: Unimicron Technology Corp.
Inventor： Shih-Lian Cheng
IPC: H05K1/02
CPC classification number: H05K1/0222 , H05K1/024 , H05K2201/09536 , H05K2201/09509 , H05K2201/0959 , H05K2201/096
Abstract: A circuit board structure includes a first dielectric layer, first and second inner circuit layers, a conductive connection layer, a second dielectric layer, two third dielectric layers, third and fourth inner circuit layers, two conductive through vias, first and second annular retaining walls, two fourth dielectric layers, first and second external circuit layers, and third and fourth annular retaining walls. The conductive through vias penetrate the third and second dielectric layers and electrically connect the third and fourth inner circuit layers. The first and second annular retaining walls surround the conductive through vias and electrically connect the third and first and the fourth and second inner circuit layers. The third and fourth annular retaining walls are respectively disposed in the fourth dielectric layers and electrically connect the first external circuit layer and the third inner circuit layer and the second external circuit layer and the fourth inner circuit layer.
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Patent Agency Ranking
公开(公告)号：US20190215950A1
公开(公告)日：2019-07-11
申请号：US16358360
申请日：2019-03-19
Applicant: AT&S (China) Co. Ltd.
Inventor： Nikolaus Bauer-Öppinger , ZhaoJian Chen , Yucun Dou , Wilhelm Tamm
CPC classification number: H05K1/0206 , H05K1/0209 , H05K1/09 , H05K1/112 , H05K1/181 , H05K3/0026 , H05K3/0035 , H05K3/42 , H05K2201/09509 , H05K2201/096 , H05K2201/09781 , H05K2201/09827 , H05K2201/09854 , H05K2203/107 , H05K2203/1476
Abstract: A component carrier includes a layer stack formed of an electrically insulating structure and an electrically conductive structure. Furthermore, a bore extends into the layer stack and has a first bore section with a first diameter (D1) and a connected second bore section with a second diameter (D2) differing from the first diameter (D1). A thermally conductive material fills substantially the entire bore. The bore is in particular formed by laser drilling.
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公开(公告)号：US20190012514A1
公开(公告)日：2019-01-10
申请号：US16131247
申请日：2018-09-14
Applicant: CORNING INCORPORATED
Inventor： Yuhui Jin , Matthew Evan Wilhelm
IPC: G06K9/00 , C03C17/36 , B23K26/382 , B23K26/53 , B23K26/00 , H05K5/00 , H05K3/40 , H05K3/22 , H05K3/00 , H05K1/11 , H05K1/03 , C03C23/00 , C03C21/00 , C03C15/00 , C03B33/02 , B23K26/402 , B23K26/386 , B23K101/42 , B23K103/00
CPC classification number: G06K9/00013 , B23K26/0006 , B23K26/382 , B23K26/386 , B23K26/389 , B23K26/402 , B23K26/53 , B23K2101/42 , B23K2103/54 , C03B33/0222 , C03C15/00 , C03C17/36 , C03C17/3649 , C03C17/3668 , C03C21/002 , C03C23/0025 , H05K1/0306 , H05K1/115 , H05K3/002 , H05K3/0029 , H05K3/22 , H05K3/4038 , H05K5/0017 , H05K2201/09509 , H05K2201/10151
Abstract: A glass sensor substrate including metallizable through vias and related process is provided. The glass substrate has a first major surface, a second major surface and an average thickness of greater than 0.3 mm. A plurality of etch paths are created through the glass substrate by directing a laser at the substrate in a predetermined pattern. A plurality of through vias through the glass substrate are etched along the etch paths using a hydroxide based etching material. The hydroxide based etching material highly preferentially etches the substrate along the etch path. Each of the plurality of through vias is long compared to their diameter for example such that a ratio of the thickness of the glass substrate to a maximum diameter of each of the through vias is greater than 8 to 1.
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公开(公告)号：US20180310414A1
公开(公告)日：2018-10-25
申请号：US15876140
申请日：2018-01-20
Applicant: Albert Yeh , TRIALLIAN CORPORATION
Inventor： Albert Yeh , Nick Yang
CPC classification number: H05K3/06 , H01L21/486 , H01L23/49827 , H01L23/49838 , H01L23/49866 , H05K1/09 , H05K1/115 , H05K3/0026 , H05K3/0038 , H05K3/064 , H05K3/26 , H05K3/4084 , H05K3/424 , H05K3/425 , H05K2201/0323 , H05K2201/09509 , H05K2201/09563 , H05K2203/0392 , H05K2203/0723 , H05K2203/0759 , H05K2203/107 , H05K2203/122
Abstract: A method for manufacturing traces of a printed circuit board (PCB) comprises an application of the periodic pulse reverse (PPR) pattern plating process. In the first stage, walls and bottoms in drilled holes of the PCB are modified with reduced graphene oxide (rGO) so that the vias can be formed by filling with copper and a very thin copper layer can be formed on the substrate through the electroplating process. In the second stage, a pattern of very fine traces with width/space less than 30/30 μm is formed on the thin copper layer and then the traces are formed through the PPR pattern plating process. After removing unwanted copper layer, the traces with even thicknesses and square profiles are achieved and thus conform to requirements of the high density interconnection (HDI) technology.
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公开(公告)号：US09999137B2
公开(公告)日：2018-06-12
申请号：US14931356
申请日：2015-11-03
Applicant: Intrinsiq Materials, Inc.
Inventor： David Ciufo , Janet Heyen
IPC: H01K3/10 , H05K3/40 , H05K3/00 , H05K3/42 , H05K1/03 , H05K1/09 , H05K3/12 , H05K3/22 , H05K3/26 , H05K3/46
CPC classification number: H05K3/4069 , H05K1/0306 , H05K1/032 , H05K1/097 , H05K3/0047 , H05K3/1233 , H05K3/227 , H05K3/26 , H05K3/429 , H05K3/4617 , H05K2201/0266 , H05K2201/0347 , H05K2201/09509 , H05K2201/09536 , H05K2201/09563 , H05K2203/0139 , H05K2203/085 , H05K2203/086 , H05K2203/107 , H05K2203/1131 , H05K2203/143 , H05K2203/1438 , Y10T29/49165
Abstract: A method for filling a via on a printed circuit board formulates a paste as a dispersion of copper particulate that includes nanocopper particles in a solvent and a binder and depositing the paste into a via cavity formed in the printed circuit board. Heating the paste-filled cavity removes most of the solvent. The method sinters the deposited paste in the via cavity, planarizes the sintered via, and overplates the filled via with copper.
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公开(公告)号：US09999129B2
公开(公告)日：2018-06-12
申请号：US12590650
申请日：2009-11-12
Applicant: John S. Guzek , Mihir K. Roy , Brent M. Roberts
Inventor： John S. Guzek , Mihir K. Roy , Brent M. Roberts
IPC: H01L25/065 , H01L23/498 , H01L23/64 , H05K1/16 , H01L23/00 , H05K1/02 , H05K1/11
CPC classification number: H05K1/165 , H01L24/16 , H01L2224/16 , H01L2924/14 , H01L2924/15311 , H05K1/0254 , H05K1/0262 , H05K1/116 , H05K2201/09509 , H05K2201/09527 , H05K2201/096 , H05K2201/10378 , H05K2203/1572 , H01L2924/00
Abstract: A microelectronic device comprises a first substrate (110) having a first electrically conductive path (111) therein and a second substrate (120) above the first substrate and having a second electrically conductive path (121) therein, wherein the first electrically conductive path and the second electrically conductive path are electrically connected to each other and form a portion of a current loop (131) of an inductor (130).
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