公开(公告)号：US07605048B2

公开(公告)日：2009-10-20

申请号：US11697477

申请日：2007-04-06

Applicant: Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

Inventor： Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

IPC: H01L21/20 ,  H01G4/228

CPC classification number: H05K1/162 ,  H01G4/008 ,  H01G4/33 ,  H05K3/382 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315 ,  H05K2203/1536 ,  Y10T29/43

Abstract: High capacitance value capacitors are formed using bimetal foils of an aluminum layer attached to a copper layer. The copper side of a bimetallic copper/aluminum foil or a monometallic aluminum foil is temporarily protected using aluminum or other materials, to form a sandwich. The exposed aluminum is treated to increase the surface area of the aluminum by at least one order of magnitude, while not attacking any portion of the protected metal. When the sandwich is separated, the treated bimetal foil is formed into a capacitor, where the copper layer is one electrode of the capacitor and the treated aluminum layer is in intimate contact with a dielectric layer of the capacitor.

Abstract translation: 使用连接到铜层的铝层的双金属箔形成高电容值电容器。 双金属铜/铝箔或单金属铝箔的铜面用铝或其他材料暂时保护，形成三明治。 处理暴露的铝以将铝的表面积增加至少一个数量级，同时不侵蚀受保护金属的任何部分。 当三明治分离时，处理的双金属箔形成电容器，其中铜层是电容器的一个电极，并且经处理的铝层与电容器的电介质层紧密接触。

公开(公告)号：US20090242256A1

公开(公告)日：2009-10-01

申请号：US12410685

申请日：2009-03-25

Applicant: Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

Inventor： Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/098

Abstract: In a dielectric element, the angle θ made by either the top face or the bottom face and the side faces is either 0°

Abstract translation: 在电介质元件中，由顶面或底面和侧面形成的角度θ为0°<89°，或91°<180°，并且为89°以外的角度 <=θ<= 91°。 通过这种方式，介电元件的侧面与玻璃环氧树脂基板和绝缘材料的接触面积增加，与树脂基板的粘附性提高，并且当埋在两个树脂之间时，可以提高强度和可靠性 底物。

公开(公告)号：US07594320B2

公开(公告)日：2009-09-29

申请号：US11260077

申请日：2005-10-27

Applicant: Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

Inventor： Masaru Takada ,  Hiroyuki Kobayashi ,  Kenji Chihara ,  Hisashi Minoura ,  Kiyotaka Tsukada ,  Mitsuhiro Kondo

IPC: H01K3/10 ,  H05K3/10

CPC classification number: H01L24/32 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K1/116 ,  H05K3/0008 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/242 ,  H05K3/243 ,  H05K3/28 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09381 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/0959 ,  H05K2201/09781 ,  H05K2203/0554 ,  H05K2203/0571 ,  H05K2203/107 ,  H05K2203/175 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.

Abstract translation: 在具有导体电路（6）的绝缘板（7）的表面上印刷包括热固性树脂的阻焊剂。 然后将阻焊剂热固化以形成具有低热膨胀系数的绝缘膜（1）。 然后将激光束（2）施加到要形成开口的绝缘膜的部分，以烧掉用于形成开口（10）的相同部分，由此导体电路（6）暴露。 该开口可以通过在其内表面上形成金属电镀膜而形成为导电孔。 优选地，形成外部连接垫以覆盖开口。 通过使用在电镀完成后优选用激光束切断的电镀铅来形成金属涂膜。

公开(公告)号：US20090230541A1

公开(公告)日：2009-09-17

申请号：US12395008

申请日：2009-02-27

Applicant: Makoto Araki ,  Shimpei Ishida ,  Shigeru Nakamura

Inventor： Makoto Araki ,  Shimpei Ishida ,  Shigeru Nakamura

IPC: H01L23/48 ,  H01L21/78 ,  H01L21/50

CPC classification number: H01L24/91 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/92 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/186 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2203/049 ,  H01L2224/81 ,  H01L2224/82 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device in which a chip is embedded in a wiring board and bump electrodes formed over the front surface of the semiconductor chip are flip-chip coupled to wiring formed in the wiring board and the entire back surface of the semiconductor chip functions well as a back electrode and a method of manufacturing the semiconductor device. A semiconductor chip is embedded inside a wiring board. The semiconductor chip is flip-chip coupled (face down) to a base substrate as the core layer of the wiring board through bump electrodes. A conductive film is formed over the semiconductor chip's surface reverse to the surface over which bump electrodes are formed. The conductive film functions as a back electrode which supplies a reference voltage to the integrated circuit in the semiconductor chip. The conductive film is electrically coupled to third-layer wiring through vias.

Abstract translation: 其中将芯片嵌入布线板中的半导体器件和形成在半导体芯片的前表面上的凸块电极被倒装芯片耦合到布线板中形成的布线，并且半导体芯片的整个背面的功能很好地作为 背电极和半导体器件的制造方法。 将半导体芯片嵌入在布线板内。 半导体芯片通过凸块电极与布线板的芯层作为基底衬底（面向下）耦合（面向下）。 导电膜形成在与形成凸起电极的表面相反的半导体芯片的表面上。 导电膜用作向半导体芯片中的集成电路提供参考电压的背面电极。 导电膜通过通孔电耦合到第三层布线。

公开(公告)号：US07585419B2

公开(公告)日：2009-09-08

申请号：US11154695

申请日：2005-06-17

Applicant: Joseph Cheng

Inventor： Joseph Cheng

IPC: H01B13/00 ,  B44C1/22

CPC classification number: H05K1/114 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/181 ,  H05K1/113 ,  H05K3/20 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/0959 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A substrate structure and the fabrication method thereof are provided herein. The present invention utilizes a laminate as the support of the package process and then removes the laminate after the following package steps so as to obtain a quite smooth surface for using in the internal-plane structure of the circuit board and a stacking structure that can be applied to many different types of the chip package structures.

Abstract translation: 本文提供了一种衬底结构及其制造方法。 本发明采用叠层作为包装工艺的支撑体，然后在以下包装步骤之后移除层压板，以获得在电路板的内部平面结构中使用的非常光滑的表面和可以 适用于许多不同类型的芯片封装结构。

公开(公告)号：US20090205852A1

公开(公告)日：2009-08-20

申请号：US12193460

申请日：2008-08-18

Applicant: Chun-Chien Chen ,  Tsung-Yuan Chen

Inventor： Chun-Chien Chen ,  Tsung-Yuan Chen

IPC: H05K1/00 ,  H05K3/02

CPC classification number: H05K3/44 ,  H05K3/20 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/445 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/0369 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.

Abstract translation: 提供电路板的制造方法。 提供金属芯。 在一些载体的每一个上形成导电层。 载体和电介质层被层叠在金属芯的两侧以形成堆叠结构。 每个电介质层位于相应的载体和金属芯之间，并且导电层的一部分嵌入相应的介电层中。 然后，移除载体。 在堆叠结构中形成盲通孔和/或通孔，以将相应的导电层和金属芯连接和/或连接金属芯两侧的导电层，其中通孔穿过金属芯 。 去除介电层表面上的导电层。

公开(公告)号：US20090200658A1

公开(公告)日：2009-08-13

申请号：US12427668

申请日：2009-04-21

Applicant: Shih Ping HSU ,  Chung Cheng LIEN ,  Shang Wei CHEN

Inventor： Shih Ping HSU ,  Chung Cheng LIEN ,  Shang Wei CHEN

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract translation: 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US07531011B2

公开(公告)日：2009-05-12

申请号：US11272688

申请日：2005-11-15

Applicant: Tomoo Yamasaki

Inventor： Tomoo Yamasaki

IPC: H01G9/00

CPC classification number: H05K1/162 ,  H01G4/10 ,  H01G4/38 ,  H01L23/49816 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0191 ,  H05K2201/09509 ,  H05K2203/0315 ,  H05K2203/1476 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435

Abstract: In a capacitor device of the present invention includes a substrate, a plurality of lower electrodes formed on the substrate, a plurality of dielectric films formed on a plurality of lower electrodes respectively in a state that the dielectric films are separated mutually, and upper electrodes formed on a plurality of dielectric films respectively, a plurality of capacitors each composed of the lower electrode, the dielectric film, and the upper electrode are arranged on the substrate respectively, and each of the dielectric films in a plurality of capacitors has a different film thickness.

Abstract translation: 在本发明的电容器装置中，包括基板，形成在基板上的多个下电极，分别在电介质膜相互分离的状态下分别形成在多个下电极上的多个电介质膜，形成上电极 在多个电介质膜上分别配置有分别由下部电极，电介质膜和上部电极构成的多个电容器，多个电容器中的各个电介质膜具有不同的膜厚 。

公开(公告)号：US07530163B2

公开(公告)日：2009-05-12

申请号：US11285347

申请日：2005-11-23

Applicant: Masahiro Sunohara ,  Kei Murayama ,  Naohiro Mashino ,  Mitsutoshi Higashi

Inventor： Masahiro Sunohara ,  Kei Murayama ,  Naohiro Mashino ,  Mitsutoshi Higashi

IPC: H05K3/30

CPC classification number: H05K1/185 ,  H01L21/78 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/81 ,  H01L24/82 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/16237 ,  H01L2224/24051 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/81192 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/92244 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K3/4602 ,  H05K2201/09509 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05655 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171

Abstract: There is provided a electronic parts packaging structure that includes a mounted body on which an electronic parts is mounted, the electronic parts having a connection pad, which has an etching stopper film (a copper film, a gold film, a silver film, or a conductive past film) as an uppermost film, and mounted on the mounted body to direct the connection pad upward, an interlayer insulating film for covering the electronic parts, a via hole formed in the insulating film on the connection pad of the electronic parts, and a wiring pattern connected to the connection pad via the via hole.

Abstract translation: 提供一种电子部件包装结构，其包括安装有电子部件的安装体，电子部件具有连接焊盘，该连接焊盘具有蚀刻停止膜（铜膜，金膜，银膜或 导电过去膜），并且安装在安装体上以将连接焊盘向上引导，用于覆盖电子部件的层间绝缘膜，形成在电子部件的连接焊盘上的绝缘膜中的通孔，以及 通过通孔连接到连接焊盘的布线图案。

公开(公告)号：US07516545B2

公开(公告)日：2009-04-14

申请号：US11591586

申请日：2006-11-02

Applicant: Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

Inventor： Myung Sam Kang ,  Shuhichi Okabe ,  Jung Hyun Park ,  Hoe Ku Jung ,  Ji Eun Kim

IPC: H01K3/10 ,  H05K3/02

CPC classification number: H05K1/116 ,  H05K3/0094 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/0959 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/0542 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49133 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of manufacturing a printed circuit board having a landless via hole. Specifically, this invention provides a method of manufacturing a printed circuit board having a landless via hole without the upper land of a via hole using a photoresist (P-LPR) which is loaded in the via hole. Therefore, in this invention, since a circuit pattern is formed using only copper of a copper clad laminate, the width thereof is minimized, thus easily realizing a fine circuit pattern. Further, the landless via hole structure is applied, resulting in a highly dense circuit pattern.

Abstract translation: 公开了一种具有无地过孔的印刷电路板的制造方法。 具体而言，本发明提供一种制造印刷电路板的方法，所述印刷电路板具有无通孔通孔，所述无通孔通孔使用装载在所述通孔中的光致抗蚀剂（P-LPR）而不具有通孔的上部焊盘。 因此，在本发明中，由于仅使用覆铜层压板的铜形成电路图案，所以其宽度被最小化，因此容易实现精细电路图案。 此外，施加无地通孔结构，导致高度密集的电路图案。