Patent search cpc:"H01L2224/83005" Page 5

41.

发明申请
Discrete Polymer in Fan-Out Packages 审中-公开

公开(公告)号：US20180090465A1

公开(公告)日：2018-03-29

申请号：US15830458

申请日：2017-12-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen , Jie Chen

IPC: H01L25/065 , H01L25/00 , H01L21/48 , H01L21/56 , H01L21/78 , H01L23/538 , H01L23/31

CPC classification number: H01L25/0652 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/565 , H01L21/568 , H01L21/76802 , H01L21/76831 , H01L21/78 , H01L23/3114 , H01L23/3135 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/50 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2224/97 , H01L2225/06517 , H01L2225/06548 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2924/18162 , H01L2224/83

Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

42.

发明申请
STACKED TYPE CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开

公开(公告)号：US20180076179A1

公开(公告)日：2018-03-15

申请号：US15640595

申请日：2017-07-03

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu , Nan-Chun Lin , Shang-Yu Chang Chien

IPC: H01L25/065 , H01L21/56 , H01L25/00 , H01L23/31 , H01L23/00 , H01L23/522

CPC classification number: H01L25/0657 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L23/3107 , H01L23/3128 , H01L23/5226 , H01L24/14 , H01L24/17 , H01L24/32 , H01L25/03 , H01L25/50 , H01L2221/68327 , H01L2221/6834 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/73267 , H01L2224/81005 , H01L2224/83005 , H01L2224/92244 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06527 , H01L2225/06548 , H01L2225/06568 , H01L2225/06586 , H01L2924/01028 , H01L2924/01029 , H01L2924/0132 , H01L2924/15311 , H01L2924/18161 , H01L2924/18162 , H01L2224/214 , H01L2924/00

Abstract: A stacked-type chip package structure includes a first chip, first terminals, a first redistribution layer, a first encapsulant, a second chip, second terminals, a second redistribution layer and through pillars. Each first chip includes a first active surface and first pads located on the first active surface. The first terminals are disposed on the first pads. The first redistribution layer is electrically connected to the first chip. The first encapsulant encapsulates the first chip and exposes top surfaces of the first terminals. The second chip is disposed over the first encapsulant. The second chip includes a second active surface and second pads located on the second active surface. The second terminals are disposed on the second pads. The second redistribution layer is electrically connected to the second chip. The through pillars electrically connect the first redistribution layer and the second redistribution layer.

43.

发明申请
METHODS FOR PRODUCING SEMICONDUCTOR DEVICES 审中-公开

公开(公告)号：US20180076090A1

公开(公告)日：2018-03-15

申请号：US15818913

申请日：2017-11-21

Applicant: Infineon Technologies Austria AG

Inventor： Andreas Voerckel

IPC: H01L21/82 , H01L23/00 , H01L21/56 , H01L21/683 , H01L21/768 , H01L23/32 , H01L21/48

CPC classification number: H01L21/82 , H01L21/4846 , H01L21/56 , H01L21/568 , H01L21/6835 , H01L21/76838 , H01L23/32 , H01L24/83 , H01L2221/68327 , H01L2224/32245 , H01L2224/83005 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/181 , H01L2924/00

Abstract: A method for producing a semiconductor device in accordance with various embodiments may include providing a semiconductor workpiece attached to a first carrier; dicing the semiconductor workpiece and the carrier so as to form at least one individual semiconductor chip; mounting the at least one semiconductor chip with a side facing away from the carrier, to an additional carrier.

44.

发明申请
METHOD FOR FORMING A PACKAGE STRUCTURE INCLUDING FORMING A MOLDING COMPOUND ON FIRST LARGER BUMPS SURROUNDING A SEMICONDUCTOR DIE AND SECOND SMALLER BUMPS FORMED UNDER THE SEMICONDUCTOR DIE 审中-公开

公开(公告)号：US20180053745A1

公开(公告)日：2018-02-22

申请号：US15240422

申请日：2016-08-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Jen CHENG , Yu-Chih HUANG , Chih-Hua CHEN , Yu-Feng CHEN , Hao-Yi TSAI

IPC: H01L25/065 , H01L23/538 , H01L21/56

CPC classification number: H01L25/0657 , H01L21/56 , H01L21/6835 , H01L21/6836 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2221/68327 , H01L2221/68359 , H01L2221/68372 , H01L2221/68381 , H01L2224/0401 , H01L2224/1403 , H01L2224/16145 , H01L2224/16227 , H01L2224/73204 , H01L2224/81005 , H01L2224/81815 , H01L2224/83005 , H01L2224/92125 , H01L2224/92244 , H01L2224/97 , H01L2225/06513 , H01L2225/06568 , H01L2225/1035 , H01L2225/1058 , H01L2924/14 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/18161 , H01L2224/83

Abstract: Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.

45.

发明申请
WIRING BOARD 审中-公开

公开(公告)号：US20180047661A1

公开(公告)日：2018-02-15

申请号：US15663962

申请日：2017-07-31

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Kazuhiro OSHIMA , Hiroharu YANAGISAWA , Kazuhiro KOBAYASHI , Katsuya FUKASE , Ken MIYAIRI

IPC: H01L23/498 , H01L21/48 , H01L23/16

CPC classification number: H01L23/49822 , H01L21/4857 , H01L21/561 , H01L21/568 , H01L23/145 , H01L23/16 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L2224/13111 , H01L2224/13116 , H01L2224/16227 , H01L2224/16238 , H01L2224/26175 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/92125 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/19105 , H01L2924/3511 , H01L2224/81 , H01L2224/83 , H01L2924/01029 , H01L2924/01047

Abstract: A wiring board includes an insulating layer including a first insulating film provided with a first surface and a second surface that is opposite to the first surface, and composed of only resin, and a second insulating film provided with a first surface and a second surface that is opposite to the first surface, including a reinforcing member and resin, in which the reinforcing member is impregnated with the resin, and stacked on the first surface of the first insulating film such that the second surface of the second insulating film contacts the first surface of the first insulating film and the second surface of the first insulating film is exposed outside; and a first wiring layer embedded in the first insulating film, a predetermined surface of the first wiring layer being exposed from the second surface of the first insulating film.

46.

发明授权
Double-sided semiconductor package and dual-mold method of making same 有权

公开(公告)号：US09893017B2

公开(公告)日：2018-02-13

申请号：US15089151

申请日：2016-04-01

Applicant: STATS ChipPAC, Ltd.

Inventor： Il Kwon Shim , Pandi C. Marimuthu , Yaojian Lin

IPC: H01L23/538 , H01L21/48 , H01L25/10 , H01L21/56 , H01L21/683 , H01L23/31 , H01L23/00 , H01L25/16

CPC classification number: H01L23/5389 , H01L21/486 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3128 , H01L23/5384 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/97 , H01L25/105 , H01L25/16 , H01L2221/68327 , H01L2221/6834 , H01L2221/68345 , H01L2221/68359 , H01L2221/68381 , H01L2224/0401 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/16227 , H01L2224/24195 , H01L2224/2919 , H01L2224/2929 , H01L2224/2939 , H01L2224/32225 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2224/83 , H01L2224/83005 , H01L2224/83192 , H01L2224/85 , H01L2224/85005 , H01L2224/92164 , H01L2224/92244 , H01L2224/92247 , H01L2224/94 , H01L2224/97 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00012 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/3025 , H01L2924/3511 , H01L2224/03 , H01L2924/00014 , H01L2924/00 , H01L2224/32245 , H01L2224/48247

Abstract: A semiconductor device comprises a first conductive layer formed on a carrier over an insulating layer. A portion of the insulating layer is removed prior to forming the first conductive layer. A first semiconductor die is disposed over the first conductive layer. A discrete electrical component is disposed over the first conductive layer adjacent to the first semiconductor die. A first encapsulant is deposited over the first conductive layer and first semiconductor layer. A conductive pillar is formed through the first encapsulant between the first conductive layer and second conductive layer. A second encapsulant is deposited around the first encapsulant, first conductive layer, and first semiconductor die. A second conductive layer is formed over the first semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer. The carrier is removed after forming the second conductive layer. A semiconductor package is mounted to the first conductive layer.

47.

发明授权
Wafer level flat no-lead semiconductor packages and methods of manufacture 有权

公开(公告)号：US09892952B2

公开(公告)日：2018-02-13

申请号：US14341454

申请日：2014-07-25

Applicant: Semiconductor Components Industries, LLC

Inventor： Darrell Truhitte , James P. Letterman, Jr.

IPC: H01L21/683 , H01L23/31 , H01L21/56 , H01L21/48 , H01L23/00 , H01L23/36 , H01L23/495

CPC classification number: H01L21/6835 , H01L21/4832 , H01L21/561 , H01L21/568 , H01L21/6836 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/36 , H01L23/49537 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/49 , H01L24/75 , H01L24/81 , H01L24/83 , H01L24/85 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L2221/68304 , H01L2221/68327 , H01L2221/68377 , H01L2221/68381 , H01L2224/04105 , H01L2224/11 , H01L2224/11003 , H01L2224/11312 , H01L2224/1132 , H01L2224/11334 , H01L2224/11418 , H01L2224/1146 , H01L2224/11462 , H01L2224/116 , H01L2224/119 , H01L2224/1308 , H01L2224/131 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/1319 , H01L2224/16245 , H01L2224/16258 , H01L2224/27003 , H01L2224/27312 , H01L2224/2732 , H01L2224/27334 , H01L2224/27418 , H01L2224/2746 , H01L2224/27462 , H01L2224/276 , H01L2224/279 , H01L2224/2908 , H01L2224/291 , H01L2224/29124 , H01L2224/29139 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/29164 , H01L2224/29166 , H01L2224/2919 , H01L2224/32245 , H01L2224/32258 , H01L2224/33181 , H01L2224/45015 , H01L2224/48091 , H01L2224/4811 , H01L2224/48111 , H01L2224/48145 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2224/73204 , H01L2224/73265 , H01L2224/75251 , H01L2224/75252 , H01L2224/753 , H01L2224/75755 , H01L2224/75756 , H01L2224/81192 , H01L2224/8121 , H01L2224/81805 , H01L2224/81815 , H01L2224/81856 , H01L2224/83 , H01L2224/83005 , H01L2224/83191 , H01L2224/83192 , H01L2224/8321 , H01L2224/83805 , H01L2224/83815 , H01L2224/83856 , H01L2224/85005 , H01L2224/92 , H01L2224/92125 , H01L2224/92147 , H01L2224/92227 , H01L2224/94 , H01L2224/95 , H01L2224/97 , H01L2924/00014 , H01L2924/181 , H01L2924/3511 , H01L2924/0665 , H01L2924/014 , H01L2224/81 , H01L2224/27 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2924/207

Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.

48.

发明授权
Fan-out semiconductor package structure and fabricating method 有权

公开(公告)号：US09887148B1

公开(公告)日：2018-02-06

申请号：US15437444

申请日：2017-02-21

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Jen-I Huang , Ching-Yang Chen

IPC: H01L23/04 , H01L23/485 , H01L23/31 , H01L21/56

CPC classification number: H01L23/485 , H01L21/568 , H01L23/145 , H01L23/3121 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L2224/0401 , H01L2224/16237 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/83005 , H01L2224/92125 , H01L2924/15313 , H01L2924/1533

Abstract: A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.