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公开(公告)号：US09704565B2
公开(公告)日：2017-07-11
申请号：US15012970
申请日：2016-02-02
发明人： Wei-Cheng Wu , Wei Min Chan , Yen-Huei Chen , Hung-Jen Liao , Ping-Wei Wang
IPC分类号： G11C11/40 , G11C11/419 , G11C11/4063 , G11C11/409 , G11C11/412
CPC分类号： G11C11/419 , G11C11/4063 , G11C11/409 , G11C11/412
摘要： A method of using a static random access memory (SRAM) includes pre-discharging a data line to a reference voltage, activating a bit cell connected to the data line, wherein the bit cell comprises a p-type pass gate, and exchanging bit information between the data line and the activated bit cell.
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公开(公告)号：US20170178983A1
公开(公告)日：2017-06-22
申请号：US15449683
申请日：2017-03-03
发明人： Tzuan-Horng Liu , Chen-Hua Yu , Hsien-Pin Hu , Tzu-Yu Wang , Wei-Cheng Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L21/66 , G01R1/073 , H01L21/48 , H01L23/498 , H01L23/58
CPC分类号： H01L22/32 , G01R1/07378 , H01L21/4853 , H01L21/486 , H01L21/561 , H01L21/6835 , H01L22/30 , H01L22/34 , H01L23/49811 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5226 , H01L23/585 , H01L2221/68331 , H01L2224/05001 , H01L2224/05026 , H01L2224/05572 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/01322 , H01L2924/15311 , H01L2924/00014 , H01L2224/81 , H01L2924/00 , H01L2224/05124 , H01L2224/05147
摘要： An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
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公开(公告)号：US20170084529A1
公开(公告)日：2017-03-23
申请号：US15357205
申请日：2016-11-21
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC分类号： H01L23/498 , H01L23/31
CPC分类号： H01L23/49838 , H01L23/3171 , H01L23/3192 , H01L23/498 , H01L23/49827 , H01L23/522 , H01L23/528 , H01L23/5329 , H01L23/585 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/05681 , H01L2224/11849 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10336 , H01L2924/10337 , H01L2924/10338 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/14 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11
摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
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64.发明授权Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate packages 有权晶圆片上基板封装上的晶片过程控制监控公开(公告)号：US09581638B2
公开(公告)日：2017-02-28
申请号：US13905958
申请日：2013-05-30
发明人： Wei-Cheng Wu , Li-Han Hsu , Sao-Ling Chiu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Lin
CPC分类号： H01L22/14 , G01R1/07314 , G01R31/265 , G01R31/2884 , H01L22/12 , H01L22/32 , H01L24/17 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/16055 , H01L2224/16113 , H01L2224/16145 , H01L2224/16146 , H01L2224/16227 , H01L2224/16235 , H01L2224/1713 , H01L2225/06513 , H01L2225/06541 , H01L2225/06596
摘要： An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure design comprises placing a testing structure in a pre-selected area a top die in the CoW structure, and electrically testing a plurality of microbumps in the CoW structure by applying a universal testing probe card to the testing structure.
摘要翻译： 一种实施方式包括提供晶片芯片（CoW）结构的标准化测试结构设计，其中标准化测试结构设计包括将测试结构放置在CoW结构中的顶部模具的预选区域内，并且电测试 通过在测试结构上应用通用测试探针卡，在CoW结构中的多个微胶片。
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公开(公告)号：US09502343B1
公开(公告)日：2016-11-22
申请号：US14858558
申请日：2015-09-18
发明人： Cheng-Hsien Hsieh , Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Li-Han Hsu , Wei-Cheng Wu
IPC分类号： H01L23/52 , H01L23/498 , H01L23/31
CPC分类号： H01L23/49838 , H01L23/3171 , H01L23/3192 , H01L23/498 , H01L23/49827 , H01L23/522 , H01L23/528 , H01L23/5329 , H01L23/585 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05572 , H01L2224/05666 , H01L2224/05681 , H01L2224/11849 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/94 , H01L2924/10252 , H01L2924/10253 , H01L2924/10271 , H01L2924/1032 , H01L2924/10336 , H01L2924/10337 , H01L2924/10338 , H01L2924/10339 , H01L2924/10342 , H01L2924/10351 , H01L2924/14 , H01L2924/3512 , H01L2924/014 , H01L2924/00014 , H01L2224/03 , H01L2224/11
摘要： A structure includes a metal pad, a passivation layer having a portion covering edge portions of the metal pad, and a dummy metal plate over the passivation layer. The dummy metal plate has a plurality of through-openings therein. The dummy metal plate has a zigzagged edge. A dielectric layer has a first portion overlying the dummy metal plate, second portions filling the first plurality of through-openings, and a third portion contacting the first zigzagged edge.
摘要翻译： 一种结构包括金属焊盘，具有覆盖金属焊盘的边缘部分的部分的钝化层以及钝化层上的虚设金属板。 虚拟金属板在其中具有多个通孔。 虚拟金属板具有锯齿形边。 电介质层具有覆盖在虚拟金属板上的第一部分，填充第一多个通孔的第二部分和与第一锯齿状边缘接触的第三部分。
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公开(公告)号：US20160283639A1
公开(公告)日：2016-09-29
申请号：US15174795
申请日：2016-06-06
发明人： Tzu-Yu Wang , Wei-Cheng Wu , Kuo-Ching Hsu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5009 , G06F17/5081 , G06F2217/02 , G06F2217/06 , G06F2217/08 , G06F2217/38 , G06F2217/40 , H01L24/11 , H01L24/13 , H01L2224/13005 , H01L2224/16227 , H01L2924/15311
摘要： Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern.
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67.发明申请Semiconductor Device Packages, Packaging Methods, and Packaged Semiconductor Devices 有权半导体器件封装，封装方法和封装半导体器件公开(公告)号：US20160013138A1
公开(公告)日：2016-01-14
申请号：US14755700
申请日：2015-06-30
发明人： Hsien-Wei Chen , Chi-Hsi Wu , Chen-Hua Yu , Der-Chyang Yeh , Wei-Cheng Wu , Chien-Fu Tseng
IPC分类号： H01L23/00 , H01L23/31 , H01L21/768 , H01L21/56 , H01L21/78 , H01L23/12 , H01L23/522
CPC分类号： H01L21/568 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/76838 , H01L21/78 , H01L23/12 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L23/544 , H01L23/562 , H01L23/585 , H01L24/06 , H01L24/19 , H01L24/20 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2221/68372 , H01L2223/5442 , H01L2223/54426 , H01L2223/54486 , H01L2224/04042 , H01L2224/04105 , H01L2224/12105 , H01L2224/2518 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2225/0651 , H01L2225/06568 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/14 , H01L2924/1431 , H01L2924/1433 , H01L2924/1434 , H01L2924/1436 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/18165 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599 , H01L2224/85399
摘要： Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material around the integrated circuit die mounting region. An interconnect structure is over the molding material and the integrated circuit die mounting region. A protection pattern is in a perimeter region of the package around the interconnect structure. The protection pattern includes a first conductive feature that is vertical within the package near a second conductive feature. The first conductive feature has a first width, and the second conductive feature has a second width. The second width is greater than the first width.
摘要翻译： 公开了半导体器件封装，封装方法和封装半导体器件。 在一些实施例中，用于半导体器件的封装包括集成电路管芯安装区域和围绕集成电路管芯安装区域的成型材料。 互连结构在成型材料和集成电路管芯安装区域之上。 保护图案位于互连结构周围的封装的周边区域中。 保护图案包括在第二导电特征附近的封装内的垂直的第一导电特征。 第一导电特征具有第一宽度，并且第二导电特征具有第二宽度。 第二宽度大于第一宽度。
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公开(公告)号：US09116203B2
公开(公告)日：2015-08-25
申请号：US14331791
申请日：2014-07-15
发明人： Wei-Cheng Wu , Hsien-Pin Hu , Shang-Yun Hou , Shin-Puu Jeng , Chen-Hua Yu , Chao-Hsiang Yang
CPC分类号： G01R31/2896 , G01R1/0416 , G01R31/2601 , G01R31/2884 , G01R31/2886 , G01R31/2889 , G01R31/2893 , H01L22/32 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/02377 , H01L2224/0392 , H01L2224/0401 , H01L2224/05027 , H01L2224/05147 , H01L2224/05552 , H01L2224/05568 , H01L2224/05655 , H01L2224/0614 , H01L2224/0616 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13005 , H01L2224/13083 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/14131 , H01L2224/16238 , H01L2924/20752 , H01L2924/00012 , H01L2924/00014 , H01L2924/01047 , H01L2924/014
摘要： A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.
摘要翻译： 一种测试结构，其包括将芯片和基板电连接的微型阵列阵列，其中微胶片阵列的每个微型块的宽度等于或小于约50微米（μm）。 测试结构还包括连接到微丸阵列的互连结构。 该测试结构进一步包括围绕微胶片阵列周边的测试焊盘的阵列，其中测试焊盘阵列的测试焊盘通过互连结构连接到微胶片阵列的对应微型块。 测试垫的宽度大于对应的微型块的宽度，并且测试垫适于在通过钝化材料的电路探测之后被覆盖以防止颗粒和腐蚀问题。
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公开(公告)号：US11955439B2
公开(公告)日：2024-04-09
申请号：US18155672
申请日：2023-01-17
发明人： Wei-Cheng Wu , Chien-Chia Chiu , Cheng-Hsien Hsieh , Li-Han Hsu , Meng-Tsan Lee , Tsung-Shu Lin
IPC分类号： H01L23/552 , H01L21/56 , H01L21/76 , H01L21/768 , H01L23/00 , H01L23/31 , H01L23/488 , H01L23/538
CPC分类号： H01L23/552 , H01L21/56 , H01L21/76802 , H01L21/76877 , H01L23/31 , H01L23/488 , H01L23/5384 , H01L24/14
摘要： A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.
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公开(公告)号：US11756870B2
公开(公告)日：2023-09-12
申请号：US17243600
申请日：2021-04-29
发明人： Che-Yu Yeh , Tsung-Shu Lin , Wei-Cheng Wu , Tsung-Yu Chen , Li-Han Hsu , Chien-Fu Tseng
IPC分类号： H01L23/498 , H01L23/48 , H01L25/065 , H01L23/00
CPC分类号： H01L23/49822 , H01L23/481 , H01L23/49816 , H01L23/49838 , H01L24/20 , H01L24/24 , H01L25/0652 , H01L2224/2101 , H01L2224/214 , H01L2224/2105 , H01L2224/24226 , H01L2924/182
摘要： A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.
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