公开(公告)号：US20170170135A1

公开(公告)日：2017-06-15

申请号：US15445058

申请日：2017-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Virendra R. JADHAV ,  Krystyna W. SEMKOW ,  Kamalesh K. SRIVASTAVA ,  Brian R. SUNDLOF

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05666 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/11462 ,  H01L2224/11901 ,  H01L2224/13005 ,  H01L2224/13013 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13184 ,  H01L2224/13655 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16235 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/35121 ,  H01L2924/37001 ,  H01L2924/384 ,  Y10T156/10 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions

公开(公告)号：US09224708B2

公开(公告)日：2015-12-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe Colonna ,  Perceval Coudrain

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US20150061129A1

公开(公告)日：2015-03-05

申请号：US14475249

申请日：2014-09-02

Applicant: Senju Metal Industry Co., Ltd.

Inventor： Takahiro Hattori ,  Daisuke Soma ,  lsamu Sato

IPC: H01L23/00 ,  B23K1/20

CPC classification number: B23K1/203 ,  B23K1/0016 ,  B23K1/20 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03828 ,  H01L2224/1112 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13117 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13123 ,  H01L2224/13124 ,  H01L2224/13138 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13149 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/1316 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1317 ,  H01L2224/13171 ,  H01L2224/13179 ,  H01L2224/1318 ,  H01L2224/1319 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13605 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13617 ,  H01L2224/13618 ,  H01L2224/1362 ,  H01L2224/13624 ,  H01L2224/13638 ,  H01L2224/13639 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/1366 ,  H01L2224/13671 ,  H01L2924/3651 ,  H01L2924/384 ,  H05K3/3436 ,  H05K2201/10234 ,  H05K2201/10621 ,  H05K2201/10734 ,  H05K2203/041 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01032 ,  H01L2924/01014 ,  H01L2924/01057 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01015

Abstract: A bump electrode is formed on an electrode pad using a Cu core ball in which a core material is covered with solder plating, and a board which has bump electrodes such as semiconductor chip or printed circuit board mounts such a bump electrode. Flux is coated on a substrate and the bump electrodes are then mounted on the electrode pad. In a step of heating the electrode pad and the Cu core ball to melt the solder plating, a heating rate of the substrate is set to have not less than 0.01° C./sec and less than 0.3.

Abstract translation: 在电极焊盘上使用Cu芯球形成突起电极，其中芯材被焊料覆盖，并且具有诸如半导体芯片或印刷电路板的凸起电极的板安装这样的凸块电极。 将焊剂涂覆在衬底上，然后将凸块电极安装在电极焊盘上。 在加热电极焊盘和Cu芯球以熔化焊料镀层的步骤中，将衬底的加热速率设定为不低于0.01℃/秒且小于0.3。

公开(公告)号：US20150028488A1

公开(公告)日：2015-01-29

申请号：US14339630

申请日：2014-07-24

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA

Inventor： Jean-Philippe COLONNA ,  Perceval COUDRAIN

IPC: H01L23/00 ,  H01L21/306 ,  H01L21/768

CPC classification number: H01L24/19 ,  H01L21/30604 ,  H01L21/4853 ,  H01L21/6836 ,  H01L21/7685 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/13009 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13171 ,  H01L2224/13181 ,  H01L2224/13186 ,  H01L2224/1356 ,  H01L2224/13565 ,  H01L2224/13582 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13681 ,  H01L2224/13686 ,  H01L2224/14181 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/15788 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The invention relates to a method for producing an interconnection pad on a conducting element comprising an upper face and a side wall; the method being executed from a substrate at least the upper face of which is insulating; the conducting element going through at least an insulating portion of the substrate, the method being characterized in that it comprises the sequence of the following steps: a step of embossing the conducting element, a step of forming, above the upper insulating face of the substrate, a stack of layers comprising at least one electrically conducting layer and one electrically resistive layer, a step of partially removing the electrically resistive layer, a step of electrolytic growth on the portion of the electrically conducting layer so as to form at least one interconnection pad on said conducting element.

Abstract translation: 本发明涉及一种用于在导电元件上制造互连焊盘的方法，包括上表面和侧壁; 所述方法从至少其上表面绝缘的衬底执行; 所述导电元件至少穿过所述基板的绝缘部分，所述方法的特征在于，其包括以下步骤的顺序：对所述导电元件进行压花的步骤，在所述基板的上绝缘面上方形成步骤 ，包括至少一个导电层和一个电阻层的层叠层，部分去除所述电阻层的步骤，在所述导电层的所述部分上的电解生长步骤，以便形成至少一个互连衬垫 在所述导电元件上。

公开(公告)号：US20120326322A1

公开(公告)日：2012-12-27

申请号：US13165599

申请日：2011-06-21

Applicant: Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

Inventor： Ashok V. Krishnamoorthy ,  Craig A. Stephen ,  John E. Cunningham ,  James G. Mitchell

IPC: H01L23/48 ,  B32B3/00

CPC classification number: H01L24/13 ,  H01L23/48 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10126 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/1357 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/81097 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81815 ,  H01L2224/81855 ,  Y10T428/24479 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2924/01082 ,  H01L2924/0105

Abstract: A chip package includes a substrate having a positive feature, which is defined on a surface of the substrate and which protrudes above a region on the surface proximate to the positive feature. Furthermore, the chip package includes a mechanical reinforcement mechanism defined on the substrate proximate to the positive feature that increases a lateral shear strength of the positive feature relative to the substrate. In this way, the chip package may facilitate increased reliability of a multi-chip module (MCM) that includes the chip package.

Abstract translation: 芯片封装包括具有正特征的衬底，其被限定在衬底的表面上并且突出在接近正特征的表面上的区域上方。 此外，芯片封装包括限定在靠近正特征的基板上的机械加强机构，其增加正特征相对于基板的横向剪切强度。 以这种方式，芯片封装可以促进包括芯片封装的多芯片模块（MCM）的增加的可靠性。

公开(公告)号：US20120322255A1

公开(公告)日：2012-12-20

申请号：US13161303

申请日：2011-06-15

Applicant: Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

Inventor： Ming-Da Cheng ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Tzong-Hann Yang ,  Wen-Hsiung Lu ,  Zheng-Yi Lim ,  Yi-Wen Wu ,  Chung-Shi Liu

IPC: H01L21/768

CPC classification number: H01L24/11 ,  H01L21/6836 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2224/11003 ,  H01L2224/111 ,  H01L2224/1133 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11825 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13671 ,  H01L2224/13672 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01083 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2224/11

Abstract: A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

Abstract translation: 提供一种用于形成金属凸块的系统和方法。 一个实施例包括将导电材料附着到载体介质上，然后将导电材料接触到基底的导电区域。 然后使用接合工艺将导电材料的部分结合到导电区域，以在导电区域上形成导电盖，并且去除残留的导电材料和载体介质。 回流工艺用于将导电盖重新流到导电凸块中。

公开(公告)号：US08178968B2

公开(公告)日：2012-05-15

申请号：US12207565

申请日：2008-09-10

Applicant: Nobuaki Hashimoto

Inventor： Nobuaki Hashimoto

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05024 ,  H01L2224/05026 ,  H01L2224/05548 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/13624 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/325 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/10674 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/05099

Abstract: An electronic component includes: an active surface; a plurality of external connection terminals included in the active surface; a bump electrode disposed to the active surface, the bump electrode including: an internal resin formed on the active surface as a core; and a conductive film on a surface of the internal resin, the internal resin being formed in a nearly half-cylindrical shape having a transverse section of one of a nearly semicircular shape, a nearly semielliptical shape, and a nearly trapezoidal shape and extending orthogonal to the transverse section, the transverse section being orthogonal to the active surface; and a global wiring line disposed on the active surface and connecting between the plurality of external connection terminals, and at least one of the external connection terminals being electrically connected to the conductive film.

Abstract translation: 电子部件包括：活性表面; 多个外部连接端子包括在有源表面中; 凸起电极，设置在所述活性表面上，所述凸块电极包括：形成在作为芯的所述有源表面上的内部树脂; 以及在内部树脂的表面上的导电膜，内部树脂形成为具有近似半圆形，近半椭圆形和近似梯形形状的横截面的近半圆形形状，并且延伸正交于 横截面，横截面与活动表面正交; 以及设置在所述有源表面上并连接在所述多个外部连接端子之间的全局布线，并且所述外部连接端子中的至少一个电连接到所述导电膜。

公开(公告)号：US07893533B2

公开(公告)日：2011-02-22

申请号：US11839572

申请日：2007-08-16

Applicant: Atsushi Saito

Inventor： Atsushi Saito

IPC: H01L23/48

CPC classification number: H01L24/13 ,  G02F1/13452 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05669 ,  H01L2224/13008 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/1358 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/013

Abstract: A semiconductor device includes a bump electrode including a bump made of resin, a base layer disposed on the bump, and a conductive surface layer disposed on the base layer. The base layer has ductility lower than that of the conductive surface layer and includes base regions which are spaced from each other and which are arranged at least in a top zone of the bump electrode.

Abstract translation: 半导体器件包括：凸起电极，其包括由树脂制成的凸块，设置在凸块上的基底层和设置在基底层上的导电表面层。 基底层具有低于导电表面层的延展性，并且包括彼此间隔开并且至少布置在凸块电极的顶部区域中的基极区域。

公开(公告)号：US07855137B2

公开(公告)日：2010-12-21

申请号：US12190173

申请日：2008-08-12

Applicant: Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

Inventor： Mukta G. Farooq ,  Waldemar Walter Kocon ,  Kevin Shawn Petrarca ,  Richard Paul Volant

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L24/11 ,  H01L21/76852 ,  H01L21/76885 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/1184 ,  H01L2224/13083 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/13671 ,  H01L2224/13673 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/01015 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05099

Abstract: A method of forming conductive pillars on a semiconductor wafer in which the conductive pillars are plated with a protecting coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP. Only the side of the conductive pillars are plated. The ends of the conductive pillars are free of the protective plating so that the conductive pillars can be readily joined to the pads of a packaging substrate. Also disclosed is a sidewall-protected conductive pillar having a protective coating of Ni, Co, Cr, Rh, NiP, NiB , CoWP, or CoP thereon.

Abstract translation: 在半导体晶片上形成导电柱的方法，其中导电柱镀有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。 只有导电柱的一面被电镀。 导电柱的端部没有保护电镀，使得导电柱可以容易地接合到封装基板的焊盘。 还公开了一种侧壁保护的导电柱，其上具有Ni，Co，Cr，Rh，NiP，NiB，CoWP或CoP的保护涂层。

公开(公告)号：US07375427B2

公开(公告)日：2008-05-20

申请号：US11257457

申请日：2005-10-24

Applicant: Shuichi Tanaka

Inventor： Shuichi Tanaka

IPC: H01L23/48

CPC classification number: H01L23/562 ,  G02F1/13458 ,  H01L21/563 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/91 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02377 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/114 ,  H01L2224/116 ,  H01L2224/11831 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13624 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/13666 ,  H01L2224/13671 ,  H01L2224/13684 ,  H01L2224/16225 ,  H01L2224/27825 ,  H01L2224/27831 ,  H01L2224/29008 ,  H01L2224/29013 ,  H01L2224/29017 ,  H01L2224/29023 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/29563 ,  H01L2224/2957 ,  H01L2224/29582 ,  H01L2224/29624 ,  H01L2224/29644 ,  H01L2224/29647 ,  H01L2224/29655 ,  H01L2224/29664 ,  H01L2224/29666 ,  H01L2224/29671 ,  H01L2224/29684 ,  H01L2224/29695 ,  H01L2224/30155 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01066 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/00 ,  H01L2924/01028 ,  H01L2924/01084

Abstract: A semiconductor device including a semiconductor element, an electrode pad formed on the semiconductor element, and a bump electrode conductively connected to the electrode pad which includes a resin bump formed on an active face of the semiconductor element and a conductive layer provided from the electrode pad to the surface of the resin bump, the conductive layer and the resin bump being arranged without adhesion.

Abstract translation: 包括半导体元件的半导体器件，形成在半导体元件上的电极焊盘和导电连接到电极焊盘的突起电极，该电极焊盘包括形成在半导体元件的有源面上的树脂凸块和从电极焊盘提供的导电层 到树脂凸块的表面，导电层和树脂凸块被布置而不粘附。